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NJU6818
Preliminary
80-Common X 104RGB-Segment in 4096-Color STN LCD DRIVER
GENERAL DESCRIPTION
The NJU6818 is a STN LCD driver with 80-common x 104RGB-segment in 4096-color. It consists of 312segment drivers (104xRGB), 80-common drivers, serial and parallel MPU interface circuits, internal power supply circuits, gradation palettes and 99,840-bit for graphic display data RAM. Each segment driver outputs 16-gradation level out of 32gradation level of the gradation palette. Since the NJU6818 provides low operating voltage of 1.7V and low operating current, it is ideally suited for batterypowered handheld applications.
PACKAGE OUTLINE
NJU6818CJ
FEATURES
4096-color STN LCD driver LCD drivers 80-commons, 104RGB-segments Display data RAM (DDRAM) 99,840-bit for graphic display Color display mode 16-gradation level out of 32-gradation level of the gradation palette Black & white display mode 80x312 pixels in 16-gradation level or 80x312 pixels in B&W 256-color driving mode 8/16bit parallel interface directly-connective to 68/80 series MPU Programmable 8- or 16-bit data bus length for display data 3-/4-line serial interface Programmable duty and bias ratios Programmable internal voltage booster (Maximum 6-times) Programmable contrast control using 128-step EVR Chip Identification (ID) Various instructions Display data read/write, Display ON/OFF, Reverse display ON/OFF, All pixels ON/OFF, Column address, Row address, N-line inversion, Initial display line, Initial COM line, Read-modify-write, Gradation mode control, Increment control, Data bus length, Discharge ON/OFF, Duty cycle ratio, LCD bias ratio, Boost level, EVR control, Power save ON/OFF, etc Low operating current Low logic supply voltage 1.7V to 3.3V LCD driving supply voltage 5.0V to 18.0V C-MOS technology Rectangle out look for COG Package Bumped chip / TCP
2002/08/26
-1-
Note 1) The same name PADs are shorted mutually in the LSI. Note 2) The DMY PADs are electrically open.
692: SEGA102 693: SEGB102 694: SEGC102 695: SEGA103 696: SEGB103 697: SEGC103 698: DMY106 699: DMY107 700: DMY108 701: COM40 702: COM41
NJU6818
PAD LOCATION
739: COM78 740: COM79 741: DMY109 742: DMY110 743: DMY111
744: DMY112
745: DMY113
746: DMY113
747: DMY113
748: DMY114
Chip Center Chip Size Chip Thickness Bump Size Bump Pitch Bump high Bump Material
1
80: D2 79: DMY42 78: DMY41 77: D1 76: D1 75: D0 74: D0 73: DMY40 72: DMY39 71: DMY38 70: DMY37 69: DMY36 68: VDDA 67: VDDA 66: DMY35 65: DMY34 64: RDb 63: RDb 62: DMY33 61: DMY32 60: WRb 59: WRb 58: DMY31 57: DMY30 56: DMY29 55: DMY28 54: RS 53: RS 52: DMY27 51: DMY26 50: CSb 49: CSb 48: DMY25 47: DMY24 46: DMY23 45: DMY22 44: RESb 43: RESb 42: DMY21 41: VSSA 40: VSSA 39: DMY20 38: P/S 37: P/S 36: DMY19 35: DMY18 34: VDDA 33: VDDA 32: DMY17 31: DMY16 30: SEL68 29: SEL68 28: DMY15 27: VSSA 26: VSSA 25: DMY14 24: ID3 23: ID3 22: DMY13 21: DMY12 20: DMY11 19: DMY10 18: ID2 17: ID2 16: DMY9 15: DMY8 14: ID1 13: ID1 12: DMY7 11: DMY6 10: DMY5 9: DMY4 8: ID0 7: ID0 6: DMY3 5: VDDA 4: VDDA 3: DMY2 2: DMY1 1: DMY0
: X= 0m, Y= 0m : 19.25mm x 2.50mm : 625m 25m : 26m x 120m : 45m(Min) : 17.5m(Typ.) : Au
-2-
NJU6818
186: DMY65 185: V2 178: V2 177: V1 170: V1 169: DMY64 168: VLCD
X
Alignment mark coordinates ( -9445, 1070 ) ( 9445, -1070 )
Alignment mark coordinates
123: VDD 122: DMY55 121: D15 120: D15 119: D14 118: D14 117: DMY54 116: DMY53 115: D13 114: D13 113: D12 112: D12 111: DMY52 110: DMY51 109: D11 108: D11 107: D10 106: D10 105: DMY50 104: DMY49 103: D9 102: D9 101: D8 100: D8 99: DMY48 98: VSSA 97: VSSA 96: DMY47 95: D7 94: D7 93: D6 92: D6 91: DMY46 90: DMY45 89: D5 88: D5 87: D4 86: D4 85: DMY44 84: DMY43 83: D3 82: D3 81: D2
a : 25m b : 50m
a : 50m
151: VSS 150: OSC2 149: OSC2 148: DMY62 147: DMY61 146: OSC1 145: OSC1 144: DMY60 143: DMY59 142: CLK 141: CLK 140: FR 139: FR 138: DMY58 137: DMY57 136: FLM 135: FLM 134: CL 133: CL 132: DMY56 131: VDD
a
b
Alignment mark 1
Alignment mark coordinates
b
Alignment mark 2
a
c
Alignment mark coordinates ( 9257, -1068 )
161: VLCD 160: DMY63 159: VSS
Y
-3-
381: 382: 383: 384: 385: 386: 387: 388: 389: 390: 391: 291: C3+ 290: DMY82 289: DMY81 288: C2284: C2283: DMY80 282: DMY79 281: C2+ 277: C2+ 276: DMY78 275: DMY77 274: C1-
COM1 COM0 DMY103 DMY104 DMY105 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1
263: C1+ 262: DMY74 261: DMY73 260: DMY72 259: DMY71 258: DMY70 257: VEE 249: VEE 248: VOUT 240: VOUT 239: VSSH 231: VSSH 230: DMY69 229: VBA 222: VBA 221: DMY68 220: VREF 213: VREF 212: DMY67 211: VREG
d : 50m e : 20m
187: V3
270: C1269: DMY76 268: DMY75 267: C1+
NJU6818
e
195: V4 194: V3
Alignment mark coordinates
204: VREG 203: DMY66 202: V4
Alignment mark 3
d
Alignment mark coordinates ( -9257, -1068 )
297: DMY84 296: DMY83 295: C3+
-4-
NJU6818
339: DMY99
338: DMY98
337: DMY98
336: DMY98
335: DMY97
340: 341: 342: 343: 344:
DMY100 DMY101 DMY102 COM39 COM38
334: DMY96 333: DMY95 332: DMY94 331: DMY93 330: C5326: C5325: DMY92 324: DMY91 323: C5+ 319: C5+ 318: DMY90 317: DMY89 316: C4312: C4311: DMY88 310: DMY87 309: C4+ 305: C4+ 304: DMY86 303: DMY85 302: C3298: C3-
-5-
NJU6818
PAD COORDINATES 1
Chip Size 19250m x 2500m (Chip Center 0m x 0m )
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Terminal DMY0 DMY1 DMY2 VDDA VDDA DMY3 ID0 ID0 DMY4 DMY5 DMY6 DMY7 ID1 ID1 DMY8 DMY9 ID2 ID2 DMY10 DMY11 DMY12 DMY13 ID3 ID3 DMY14 VSSA VSSA DMY15 SEL68 SEL68 DMY16 DMY17 VDDA VDDA DMY18 DMY19 P/S P/S DMY20 VSSA VSSA DMY21 RESb RESb DMY22 DMY23 DMY24 DMY25 CSb CSb DMY26 X(m) -9067.5 -9022.5 -8977.5 -8932.5 -8887.5 -8842.5 -8797.5 -8752.5 -8707.5 -8662.5 -8617.5 -8572.5 -8527.5 -8482.5 -8437.5 -8392.5 -8347.5 -8302.5 -8257.5 -8212.5 -8167.5 -8122.5 -8077.5 -8032.5 -7987.5 -7942.5 -7897.5 -7852.5 -7807.5 -7762.5 -7717.5 -7672.5 -7627.5 -7582.5 -7537.5 -7492.5 -7447.5 -7402.5 -7357.5 -7312.5 -7267.5 -7222.5 -7177.5 -7132.5 -7087.5 -7042.5 -6997.5 -6952.5 -6907.5 -6862.5 -6817.5 Y(m) -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 PAD No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Terminal DMY27 RS RS DMY28 DMY29 DMY30 DMY31 WRb WRb DMY32 DMY33 RDb RDb DMY34 DMY35 VDDA VDDA DMY36 DMY37 DMY38 DMY39 DMY40 D0/SCL D0/SCL D1/SDA D1/SDA DMY41 DMY42 D2 D2
D3/SMODE D3/SMODE
X(m) -6772.5 -6727.5 -6682.5 -6637.5 -6592.5 -6547.5 -6502.5 -6457.5 -6412.5 -6367.5 -6322.5 -6277.5 -6232.5 -6187.5 -6142.5 -6097.5 -6052.5 -6007.5 -5962.5 -5917.5 -5872.5 -5737.5 -5692.5 -5647.5 -5512.5 -5467.5 -5422.5 -5287.5 -5242.5 -5197.5 -5062.5 -5017.5 -4972.5 -4837.5 -4792.5 -4747.5 -4612.5 -4567.5 -4522.5 -4387.5 -4342.5 -4297.5 -4162.5 -4117.5 -4072.5 -3937.5 -3892.5 -3757.5 -3712.5 -3667.5 -3532.5
Y(m) -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055
DMY43 DMY44 D4/SPOL D4/SPOL D5 D5 DMY45 DMY46 D6 D6 D7 D7 DMY47 VSSA VSSA DMY48 D8 D8 D9
PAD No. 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153
Terminal D9 DMY49 DMY50 D10 D10 D11 D11 DMY51 DMY52 D12 D12 D13 D13 DMY53 DMY54 D14 D14 D15 D15 DMY55 VDD VDD VDD VDD VDD VDD VDD VDD VDD DMY56 CL CL FLM FLM DMY57 DMY58 FR FR CLK CLK DMY59 DMY60 OSC1 OSC1 DMY61 DMY62 OSC2 OSC2 VSS VSS VSS
X(m) -3487.5 -3442.5 -3307.5 -3262.5 -3217.5 -3082.5 -3037.5 -2992.5 -2857.5 -2812.5 -2767.5 -2632.5 -2587.5 -2542.5 -2407.5 -2362.5 -2317.5 -2182.5 -2137.5 -2092.5 -1957.5 -1912.5 -1867.5 -1822.5 -1777.5 -1732.5 -1687.5 -1642.5 -1597.5 -1372.5 -1327.5 -1282.5 -1147.5 -1102.5 -1057.5 -922.5 -877.5 -832.5 -697.5 -652.5 -607.5 -472.5 -427.5 -382.5 -337.5 -292.5 -157.5 -112.5 22.5 67.5 112.5
Y(m) -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055
-6-
NJU6818
PAD COORDINATES 2
Chip Size 19250m x 2500m (Chip Center 0m x 0m )
PAD No. 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 Terminal VSS VSS VSS VSS VSS VSS DMY63 VLCD VLCD VLCD VLCD VLCD VLCD VLCD VLCD DMY64 V1 V1 V1 V1 V1 V1 V1 V1 V2 V2 V2 V2 V2 V2 V2 V2 DMY65 V3 V3 V3 V3 V3 V3 V3 V3 V4 V4 V4 V4 V4 V4 V4 V4 DMY66 VREG X(m) 157.5 202.5 247.5 292.5 337.5 382.5 517.5 652.5 697.5 742.5 787.5 832.5 877.5 922.5 967.5 1012.5 1057.5 1102.5 1147.5 1192.5 1237.5 1282.5 1327.5 1372.5 1507.5 1552.5 1597.5 1642.5 1687.5 1732.5 1777.5 1822.5 1867.5 1912.5 1957.5 2002.5 2047.5 2092.5 2137.5 2182.5 2227.5 2362.5 2407.5 2452.5 2497.5 2542.5 2587.5 2632.5 2677.5 2722.5 2767.5 Y(m) -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 PAD No. 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 Terminal VREG VREG VREG VREG VREG VREG VREG DMY67 VREF VREF VREF VREF VREF VREF VREF VREF DMY68 VBA VBA VBA VBA VBA VBA VBA VBA DMY69 VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VSSH VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VEE VEE VEE VEE VEE VEE VEE X(m) 2812.5 2857.5 2902.5 2947.5 2992.5 3037.5 3082.5 3127.5 3172.5 3217.5 3262.5 3307.5 3352.5 3397.5 3442.5 3487.5 3532.5 3577.5 3622.5 3667.5 3712.5 3757.5 3802.5 3847.5 3892.5 3937.5 3982.5 4027.5 4072.5 4117.5 4162.5 4207.5 4252.5 4297.5 4342.5 4567.5 4612.5 4657.5 4702.5 4747.5 4792.5 4837.5 4882.5 4927.5 5152.5 5197.5 5242.5 5287.5 5332.5 5377.5 5422.5 Y(m) -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 PAD No. 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 Terminal VEE VEE DMY70 DMY71 DMY72 DMY73 DMY74 C1+ C1+ C1+ C1+ C1+ DMY75 DMY76 C1C1C1C1C1DMY77 DMY78 C2+ C2+ C2+ C2+ C2+ DMY79 DMY80 C2C2C2C2C2DMY81 DMY82 C3+ C3+ C3+ C3+ C3+ DMY83 DMY84 C3C3C3C3C3DMY85 DMY86 C4+ C4+ X(m) 5467.5 5512.5 5647.5 5692.5 5737.5 5782.5 5827.5 5872.5 5917.5 5962.5 6007.5 6052.5 6097.5 6142.5 6187.5 6232.5 6277.5 6322.5 6367.5 6412.5 6457.5 6502.5 6547.5 6592.5 6637.5 6682.5 6727.5 6772.5 6817.5 6862.5 6907.5 6952.5 6997.5 7042.5 7087.5 7132.5 7177.5 7222.5 7267.5 7312.5 7357.5 7402.5 7447.5 7492.5 7537.5 7582.5 7627.5 7672.5 7717.5 7762.5 7807.5 Y(m) -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055
-7-
NJU6818
PAD COORDINATES 3
Chip Size 19250m x 2500m (Chip Center 0m x 0m )
PAD No. 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 Terminal C4+ C4+ C4+ DMY87 DMY88 C4C4C4C4C4DMY89 DMY90 C5+ C5+ C5+ C5+ C5+ DMY91 DMY92 C5C5C5C5C5DMY93 DMY94 DMY95 DMY96 DMY97 DMY98 DMY98 DMY98 DMY99 DMY100 DMY101 DMY102 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 X(m) 7852.5 7897.5 7942.5 7987.5 8032.5 8077.5 8122.5 8167.5 8212.5 8257.5 8302.5 8347.5 8392.5 8437.5 8482.5 8527.5 8572.5 8617.5 8662.5 8707.5 8752.5 8797.5 8842.5 8887.5 8932.5 8977.5 9022.5 9067.5 9430 9430 9430 9430 9430 9067.5 9022.5 8977.5 8932.5 8887.5 8842.5 8797.5 8752.5 8707.5 8662.5 8617.5 8572.5 8527.5 8482.5 8437.5 8392.5 8347.5 8302.5 Y(m) -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -1055 -964 -919 -874 -829 -784 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 PAD No. 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 Terminal COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 DMY103 DMY104 DMY105 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA3 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 SEGB7 X(m) 8257.5 8212.5 8167.5 8122.5 8077.5 8032.5 7987.5 7942.5 7897.5 7852.5 7807.5 7762.5 7717.5 7672.5 7627.5 7582.5 7537.5 7492.5 7447.5 7402.5 7357.5 7312.5 7267.5 7222.5 7177.5 7132.5 7087.5 7042.5 6997.5 6952.5 6907.5 6862.5 6817.5 6772.5 6727.5 6682.5 6637.5 6592.5 6547.5 6502.5 6457.5 6412.5 6367.5 6322.5 6277.5 6232.5 6187.5 6142.5 6097.5 6052.5 6007.5 Y(m) 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 PAD No. 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 Terminal SEGC7 SEGA8 SEGB8 SEGC8 SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14 SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 SEGB24 X(m) 5962.5 5917.5 5872.5 5827.5 5782.5 5737.5 5692.5 5647.5 5602.5 5557.5 5512.5 5467.5 5422.5 5377.5 5332.5 5287.5 5242.5 5197.5 5152.5 5107.5 5062.5 5017.5 4972.5 4927.5 4882.5 4837.5 4792.5 4747.5 4702.5 4657.5 4612.5 4567.5 4522.5 4477.5 4432.5 4387.5 4342.5 4297.5 4252.5 4207.5 4162.5 4117.5 4072.5 4027.5 3982.5 3937.5 3892.5 3847.5 3802.5 3757.5 3712.5 Y(m) 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055
-8-
NJU6818
PAD COORDINATES 4
Chip Size 19250m x 2500m (Chip Center 0m x 0m )
PAD No. 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 Terminal SEGC24 SEGA25 SEGB25 SEGC25 SEGA26 SEGB26 SEGC26 SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30 SEGA31 SEGB31 SEGC31 SEGA32 SEGB32 SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39 SEGA40 SEGB40 SEGC40 SEGA41 SEGB41 X(m) 3667.5 3622.5 3577.5 3532.5 3487.5 3442.5 3397.5 3352.5 3307.5 3262.5 3217.5 3172.5 3127.5 3082.5 3037.5 2992.5 2947.5 2902.5 2857.5 2812.5 2767.5 2722.5 2677.5 2632.5 2587.5 2542.5 2497.5 2452.5 2407.5 2362.5 2317.5 2272.5 2227.5 2182.5 2137.5 2092.5 2047.5 2002.5 1957.5 1912.5 1867.5 1822.5 1777.5 1732.5 1687.5 1642.5 1597.5 1552.5 1507.5 1462.5 1417.5 Y(m) 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 PAD No. 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 Terminal SEGC41 SEGA42 SEGB42 SEGC42 SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47 SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 X(m) 1372.5 1327.5 1282.5 1237.5 1192.5 1147.5 1102.5 1057.5 1012.5 967.5 922.5 877.5 832.5 787.5 742.5 697.5 652.5 607.5 562.5 517.5 472.5 427.5 382.5 337.5 292.5 247.5 202.5 157.5 112.5 67.5 22.5 -22.5 -67.5 -112.5 -157.5 -202.5 -247.5 -292.5 -337.5 -382.5 -427.5 -472.5 -517.5 -562.5 -607.5 -652.5 -697.5 -742.5 -787.5 -832.5 -877.5 Y(m) 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 PAD No. 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 Terminal SEGC58 SEGA59 SEGB59 SEGC59 SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64 SEGB64 SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 X(m) -922.5 -967.5 -1012.5 -1057.5 -1102.5 -1147.5 -1192.5 -1237.5 -1282.5 -1327.5 -1372.5 -1417.5 -1462.5 -1507.5 -1552.5 -1597.5 -1642.5 -1687.5 -1732.5 -1777.5 -1822.5 -1867.5 -1912.5 -1957.5 -2002.5 -2047.5 -2092.5 -2137.5 -2182.5 -2227.5 -2272.5 -2317.5 -2362.5 -2407.5 -2452.5 -2497.5 -2542.5 -2587.5 -2632.5 -2677.5 -2722.5 -2767.5 -2812.5 -2857.5 -2902.5 -2947.5 -2992.5 -3037.5 -3082.5 -3127.5 -3172.5 Y(m) 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055
-9-
NJU6818
PAD COORDINATES 5
Chip Size 19250m x 2500m (Chip Center 0m x 0m )
PAD No. 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 Terminal SEGC75 SEGA76 SEGB76 SEGC76 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80 SEGA81 SEGB81 SEGC81 SEGA82 SEGB82 SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89 SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 SEGB92 X(m) -3217.5 -3262.5 -3307.5 -3352.5 -3397.5 -3442.5 -3487.5 -3532.5 -3577.5 -3622.5 -3667.5 -3712.5 -3757.5 -3802.5 -3847.5 -3892.5 -3937.5 -3982.5 -4027.5 -4072.5 -4117.5 -4162.5 -4207.5 -4252.5 -4297.5 -4342.5 -4387.5 -4432.5 -4477.5 -4522.5 -4567.5 -4612.5 -4657.5 -4702.5 -4747.5 -4792.5 -4837.5 -4882.5 -4927.5 -4972.5 -5017.5 -5062.5 -5107.5 -5152.5 -5197.5 -5242.5 -5287.5 -5332.5 -5377.5 -5422.5 -5467.5 Y(m) 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 PAD No. 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 Terminal SEGC92 SEGA93 SEGB93 SEGC93 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97 SEGC97 SEGA98 SEGB98 SEGC98 SEGA99 SEGB99 SEGC99 SEGA100 SEGB100 SEGC100 SEGA101 SEGB101 SEGC101 SEGA102 SEGB102 SEGC102 SEGA103 SEGB103 SEGC103 DMY106 DMY107 DMY108 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 X(m) -5512.5 -5557.5 -5602.5 -5647.5 -5692.5 -5737.5 -5782.5 -5827.5 -5872.5 -5917.5 -5962.5 -6007.5 -6052.5 -6097.5 -6142.5 -6187.5 -6232.5 -6277.5 -6322.5 -6367.5 -6412.5 -6457.5 -6502.5 -6547.5 -6592.5 -6637.5 -6682.5 -6727.5 -6772.5 -6817.5 -6862.5 -6907.5 -6952.5 -6997.5 -7042.5 -7087.5 -7132.5 -7177.5 -7222.5 -7267.5 -7312.5 -7357.5 -7402.5 -7447.5 -7492.5 -7537.5 -7582.5 -7627.5 -7672.5 -7717.5 -7762.5 Y(m) 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 PAD No. 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 Terminal COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 DMY109 DMY110 DMY111 DMY112 DMY113 DMY113 DMY113 DMY114 X(m) -7807.5 -7852.5 -7897.5 -7942.5 -7987.5 -8032.5 -8077.5 -8122.5 -8167.5 -8212.5 -8257.5 -8302.5 -8347.5 -8392.5 -8437.5 -8482.5 -8527.5 -8572.5 -8617.5 -8662.5 -8707.5 -8752.5 -8797.5 -8842.5 -8887.5 -8932.5 -8977.5 -9022.5 -9067.5 -9430 -9430 -9430 -9430 -9430 Y(m) 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 1055 -784 -829 -874 -919 -964
- 10 -
NJU6818
BLOCK DIAGRAM
SEGA102 SEGB102 SEGC102 SEGA103 SEGB103 SEGC103
SEGA0 SEGB0 SEGC0
SEGA1 SEGB1 SEGC1
VSS VSSA VDDA VDD VLCD, V1 -V4 C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VEE VREF VBA VREG 5
Segment Driver Gradation Circuit Data Latch Circuit
Common Driver
Shift Register
Voltage booster
COM0
VSSH
Display Data RAM (DD RAM) 80x104x(4+4+4)bit
D15 D14 D13 D12 D11 D10 I/O Buffer D9 D8 D7 D6 D5 D4/SPOL D3/SMODE D2 D1/SDA D0/SCL Chip Identification Pole Control Bus Holder RAM Interface
X Address Decoder Display Timing Generator FR FLM CL
X Address Counter
X Address Register Oscillator
Line Counter
Voltage regulator
Initial Display Line Register
Line Address Decoder
Y Address Decoder
Y Address Register
Y Address Counter
COM79
CLK OSC2 OSC1
Instruction Decoder
Register Read Control
Internal Bus
MPU Interface
CSb ID3 ID2 ID1 ID0
RS
RDb
WRb
P/S
SEL68 RESb
- 11 -
NJU6818
POWER SUPPLY CIRCUITS BLOCK DIAGRAM
Reference Voltage Generator
VBA
+ -
+ + + -
VLCD
VREG VREF + Gain Control (1x-6x)
Voltage regulator
V1
V2
E.V.R 1/2VREG
+ + -
V3
V4
EVR register
Boost level register
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VEE
Voltage Booster
VOUT
- 12 -
NJU6818
TERMINAL DESCRIPTION 1
No. 123~131 151~159 231~239 4,5 33,34 67,68 26,27 40,41 97,98 161~168 170~177 178~185 187~194 195~202 Symbol VDD VSS VSSH VDDA I/O Power Power Power Power Function Power supply for logic circuits GND for logic circuits GND for high voltage circuits This terminal is internally connected to the VDD level. * This terminal is used to fix the selection terminals to the VDD level. Note) Do not use this terminal for a main power supply. This terminal is internally connected to the VSS level. * This terminal is used to fix the selection terminals to the VSS level. Note) Do not use this terminal for a main GND. LCD driving voltages * When the internal voltage booster is not used, the external LCD driving voltages (V1 to V4 and VLCD) must be supplied on these terminals. And the external voltages must be maintained with the following relation. VSSSEL86 Status H 68 series L 80 series
VSSA
Power
VLCD V1 V2 V3 V4
Power/O
263~267 270~274 277~281 284~288 291~295 298~302 305~309 312~216 319~323 326~330 222~229 213~220 249~257 240~248 204~211 43,44 29,30
C 1+ C 1C 2+ C 2C 3+ C 3C 4+ C 4C 5+ C 5VBA VREF VEE VOUT VREG RESb SEL68
O O O O O O I Power Power/O O I I
7,8 13,14 17,18 23,24
ID0 ID1 ID2 ID3
I
Chip Identification This terminal must be fixed to "1" or "0" The NJU6818 can read ID data, which is determined by fixing ID3, ID2, ID1 and ID0 pins to "1" or "0".
- 13 -
NJU6818
TERMINAL DESCRIPTION 2
No. 74,75 Symbol D0/SCL I/O I/O Function Parallel interface: D7 to D0 : 8-bit bi-directional bus * In the parallel interface mode (P/S="1"), these terminals connect to 8-bit bi-directional MPU bus. Serial interface: SDA : Serial data SCL : Serial clock SMODE : 3-/4-line serial interface mode selection SPOL : RS polarity selection (in the 3-line serial interface mode) * In the 3-/4-line serial interface mode (P/S="0"), the D0 terminal is assigned to the SCL, and the D1 terminal to the SDA. * In the 3-line serial interface mode, the D4 terminal is assigned to the SPOL. * Serial data on the SDA is fetched at the rising edge of the SCL signal in the order of the D7, D6...D0, and the fetched data is converted into 8-bit parallel data at the falling edge of the 8th SCL signal. * The SCL signal must be set to "0" after data transmissions or during non-access. 8-bit bi-directional bus * In the 16-bit data bus mode, these terminals are assigned to the upper 8-bit data bus. * In the serial interface mode or the 8-bit data bus mode of the parallel interface, these terminals must be fixed to "1" or "0".
76,77
D1/SDA
I/O
82,83
D3/SMODE
I/O
86,87
D4/SPOL
I/O
80.81 88,89 92,93 94,95
D2 D5 D6 D7
I/O
100,101 102,103 106,107 108,109 112,113 114,115 118,119 120,121 49,50 53,54
D8 D9 D10 D11 D12 D13 D14 D15 CSb RS
I/O
I I
Chip select Active "0" Resister select *This signal distinguishes transferred data as an instruction or display data as follows.
RS Distinct. H Instruction L Display data
63,64
RDb (E)
I
80 series MPU interface (P/S="1", SEL68="0") RDb signal. Active "0". 68 series MPU interface (P/S="1", SEL68="1") Enable signal. Active "1". 80 series MPU interface (P/S="1", SEL68="0") WRb signal. Active "0". 68 series MPU interface (P/S="1", SEL68="1") R/W signal.
R/W Status H Read L Write
59,60
WRb (R/W)
I
- 14 -
NJU6818
TERMINAL DESCRIPTION 3
No. 37,38 Symbol P/S I/O I Function Parallel / serial interface mode selection
P/S Chip Select Data/ Instruction Data Read/ Write Serial clock
H L
CSb CSb
RS RS
D0 ~ D7 SDA (D1)
RDb, WRb Write only
SCL (D0)
133,134 135,136 139,140 141,142 145,146 149,150
CL FLM FR CLK OSC1 OSC2
O O O O I O
386~697
SEGA0 ~SEGA103, SEGB0 ~ SEGB103, SEGC0 ~ SEGC103
O
* Since the D15 to D5 and D2 terminals are in high impedance in the serial interface mode (P/S="0"), they must be fixed to "1" or "0". The RDb and WRb terminals also must be "1" or "0". This terminal must be opened. This terminal must be opened. This terminal must be opened. This terminal must be opened. OSC * When the internal oscillator clock is used, the OSC1 terminal must be fixed to "1" or "0", and the OSC2 terminal must be opened. When the oscillation frequency from the internal oscillator is adjusted by an external resistor between OSC1 terminal and OSC2. * When an external oscillator is used, external clock is input to the OSC1 terminal, or an external resistor is connected between the OSC1 and OSC2 terminals. Segment output
REV Mode Normal Reverse Turn-off 0 1 Turn-on 1 0
* These terminals output LCD driving waveforms in accordance with the combination of the FR signal and display data. In the B/W mode
FR signal Display data Normal display mode Reverse display mode
V2 VLCD
VLCD V2
V3 VSS
VSS V3
343~382 701~740
COM0 ~
O COM79
Common output * These terminals output LCD driving waveforms in accordance with the combination of the FR signal and scanning data.
Data H L H L FR H H L L Output level VSS V1 VLCD V4
(Terminal No. 1~3,6, 9~12, 15, 16, 19~22, 25, 28, 31, 32, 35, 36, 39, 42, 45~48, 51, 52, 55~58, 61, 62, 65, 66, 69~73, 78, 79, 84, 85, 90, 91, 96, 99, 104, 105, 110, 111, 116, 117, 122, 132, 137, 138, 143, 144, 147, 148, 160, 169, 186, 203, 212, 221, 230, 258~262, 268, 269, 275, 276, 282, 283, 289, 290, 296, 297, 303, 304, 310, 311, 317, 318, 324, 325, 331~342, 383~385, 698~700, 741~748 are dummy.)
- 15 -
NJU6818
Functional Description (1) MPU Interface
(1-1) Selection of parallel / serial interface mode The P/S terminal is used to select the parallel or serial interface mode, as shown in the following table. In the serial interface mode, it is not possible to read out display data from the DDRAM or status data from the internal registers. Table 1
P/S H L P/S mode Parallel I/F Serial I/F CSb CSb CSb RS RS RS RDb RDb WRb WRb SEL68 SEL68 SDA SDA SCL SCL Data D7-D0 (D15-D0) -
Note 1) " -" : Fix to "1" or "0". (1-2) Selection of MPU interface type In the parallel interface mode, the SEL68 terminal is used to select 68- or 80-series MPU interface type, as shown in the following table. Table 2
SEL68 H L MPU type 68 series MPU 80 series MPU CSb CSb CSb RS RS RS RDb E RDb WRb R/W WRb Data D7-D0 (D15-D0) D7-D0 (D15-D0)
(1-3) Data distinction In the parallel interface mode, the combination of the RS, RDb and WRb (R/W) signals distinguishes transferred data between the LSI and MPU as instruction or display data, as shown in the following table. Table 3
RS H H L L 68 series R/W H L H L 80 series RDb WRb L H H L L H H L Function Read out instruction data Write instruction data Read out display data Write display data
(1-4) Selection of serial interface mode In the serial interface mode, the SMODE terminal is used to select the 3- or 4-line serial interface mode, as shown in the following table. Table 4
SMODE H L Serial interface mode 3-line 4-line
- 16 -
NJU6818
(1-5) 4-line serial interface mode In the 4-line serial interface mode, when the chip select is active (CSb="0"), the SDA and the SCL are enabled. When the chip select is not active (CSb="1"), the SDA and the SCL are disabled, and the internal shift register and the counter are being initialized. 8-bit serial data on the SDA is fetched at the rising edge of the SCL signal (serial clock) in order of the D7, D6...D0, and the fetched data is converted into 8-bit parallel data at the rising edge of the 8th SCL signal. In the 4-line serial interface mode, transferred data on the SDA is distinguished as display data or instruction data in accordance with the condition of the RS signal. Table 5
RS H L Data distinction Instruction data Display data
Since the serial interface operation is sensitive to external noises, the SCL should be set to "0" after data transmissions or during non-access. To release a mal-function caused by the external noises, the chip-selected status should be released (CSb="1") after each of 8-bit data transmissions. The following figure illustrates the interface timing of the 4-line serial interface operation. CSb RS SDA SCL 1 2 Fig 1 3 4 5 6 7 8 4-line serial interface timing D7 D6 D5 D4 D3 D2 D1 VALID D0
(1-6) 3-line serial interface mode In the 3-line serial interface mode, when the chip select is active (CSb="0"), the SDA and the SCL are enabled. When the chip select is not active (CSb="1"), the SDA and the SCL are disabled, and the internal shift register and counter are being initialized. 9-bit serial data on the SDA is fetched at the rising edge of the SCL signal in order of the RS, D7, D6...D0, and the fetched data is converted into 9-bit parallel data at the rising edge of the 9th SCL signal. In the 3-line serial interface mode, data on the SDA is distinguished as display data or instruction data in accordance with the condition of the RS bit of the SDA data and the status of the SPOL, as follows. Table 6
RS L H SPOL=L Data distinction Display data Instruction data RS L H SPOL=H Data distinction Instruction data Display data
- 17 -
NJU6818
Since the serial interface operation is sensitive to external noises, the SCL must be set to "0" after data transmissions or during non-access. To release a mal-function caused by the external noises, the chip-selected status should be released (CSb="1") after each of 9-bit data transmissions. The following figure illustrates the interface timing of the 3-line serial interface operation.
CSb SDA SCL 1 2 Fig 2 3 4 5 6 7 8 9 RS D7 D6 D5 D4 D3 D2 D1 D0
3-line serial interface timing
- 18 -
NJU6818
(2) Access to the DDRAM
When the CSb signal is "0", transferred data from MPU is written into the DDRAM or the instruction register in accordance with the condition of the RS signal. When the RS signal is "1", the transferred data is distinguished as display data. After the "column address" and "row address" instructions are executed, display data can be written into the DDRAM by the "Display data write" instruction. The display data is written at the rising edge of the WRb signal in the 80 series MPU mode, or at the falling edge of the E signal in the 68 series MPU mode. Table 6
RS L H Data distinction Display RAM Data Internal Command Register
In the sequence of the "Display data read" operation, transferred data from MPU is temporarily held in the internal bus-holder, then transferred to the internal data-bus. When the "Display data read" operation is executed just after the "column address" and "row address" instructions or "Display data write" instruction, unexpected data on the bus-holder is read out at the 1st execution, then the data of designated DDRAM address is read out from the 2nd execution. For this reason, a dummy read cycle must be executed to avoid the unexpected 1st data read.
Display data write operation D0 to D15 WRb Internal Bus Holder WRb n n+1 n+2 n+3 n+4 n n+1 n+2 n+3 n+4
Display data read operation WRb D0 to D7 (D0 to D15) n Address Set n RDb Fig 3 Note) In the 16-bit data bus mode, instruction data must be 16-bit as well as the display data. Dummy Read n Data Read n Address n+1 Data Read n+1 Address n+2 Data Read n+2 Address
- 19 -
NJU6818
(3) Access to the instruction register
Each instruction resisters is assigned to each address between 0H and FH, and the content of the instruction register can be read out by the combination of the "Instruction resister address" and "Instruction resister read". WRb D0 to D7 M
Instruction resister address set
m
Instruction resister contents read
N
Instruction resister address set
n
Instruction resister contents read
RDb
Fig 4
(4) 8-/16-bit data bus length for display data (In the parallel interface mode)
The 8- or 16-bit data bus length for display data is determined by the "WLS" of the "Data bus length" instruction. In the 16-bit data bus mode, instruction data must be 16-bit (D15 to D0) as well as display data. However, for the access to the instruction register, the only lower 8-bit data (D7 to D0) of 16-bit data is valid. For the access to the DDRAM, all of the 16-bit data (D15 to D0) is valid. Table 8
WLS L H Data bus length mode 8-bit 16-bit
(5) Initial display line register
The initial display line resister specifies the line address, corresponding to the initial COM line, by the "Initial display line" instruction. The initial COM line signifies the common driver, starting scanning the display data in the DDRAM, and specified by the "Initial COM line" instruction. The line address, established in the initial display line resister, is preset into the line counter whenever the FLM signal becomes "1". At the rising edge of the CL signal, the line counter is counted-up and addressed 312-bit display data, corresponding to the counted-up line address, is latched into the data latch circuit. At the falling edge of the CL signal, the latched data outputs to the segment drivers.
- 20 -
NJU6818
(6) DDRAM Mapping
The DDRAM is capable of 1,248-bit (12-bit x 104-segment) for the column address and 80-bit for the row address. In the gradation mode, each pixel for RGB corresponds to successive 3-segment drivers, and each segment driver has 16-gradation. Therefore, the LSI can drive up to 104x80 pixels in 4096-color display (16-gradation x 16gradation x 16-gradation). In the B&W mode, only MSB data from each 4-bit display data group in the DDRAM is used. Therefore, 312x80 pixels in the B&W and 104x80 pixels in the 8-gradiation are available. The range of the column address varies depending on data bus length. The range between 00H and CFH is used in the 8-bit data bus length, and the range between 00H and 67H is in the 16-bit data bus length. In the 8-bit data bus length mode
column-address 0H 0H 7bit 1H 5bit CEH 7bit CFH 5bit
row-address
4FH
7bit
5bit column-address
7bit
5bit
ABS='1' 0H
0H 4bit
1H 8bit
CEH 4bit
CFH 8bit
row-address
4FH
4bit
8bit column-address
4bit
8bit
HSW='1' 0H
0H 8bit
1H 8bit
9AH 8bit
9BH 8bit
row-address
4FH
8bit
8bit column-address
8bit
8bit
C256='1' 0H
0H 8bit
1H 8bit
66H 8bit
67H 8bit
row-address
4FH
8bit
8bit
8bit
8bit
Fig 5
- 21 -
NJU6818
In the 16-bit data bus length mode
column-address 0H 0H 12bit 67H 12bit
row-address
4FH
12bit
12bit
Fig 6 The increments for the column address and row address are set to the auto-increment mode by programming the "AXI" and "AYI" registers of the "Increment control" instruction. In this mode, the contents of the column address and row address counters automatically increment whenever the DDRAM is accessed. The column address and row address counters, independent of the line counter. They are used to designate the column and row addresses for the display data transferred from MPU. On the other hand, the line counter is used to generate the line address, and output display data to the segment drivers, being synchronized with the display control timing of the FLM and CL signals.
- 22 -
NJU6818
(7) Window addressing mode
In addition to the above usual DDRAM addressing, it is possible to access some part of DDRAM in using the window addressing mode, in which the start and end points are designated. The start point is determined by the "column address" and "row address" instructions, and the end point is determined by the "Window end column address "and "Window end row address" instructions. The setting example of the window addressing is listed, as follows. 1. Set WIN=1, AXI=1, and AYI=1 by the "Increment control" instruction 2. Set the start point by the "column address" and "row address" instructions 3. Set the end point by the "Window end column address" and "Window end row address" instructions 4. Enable to access to the DDRAM in the window addressing mode In the window addressing mode (WIN=1, AXI=1, AYI=1), the read-modify-write operation is available by setting "0" to the "AIM" register of the "Increment control" instruction. And in the window addressing mode, the following relation for the start and end points must be maintained to avoid a malfunction. AX (column address of start point) < EX (column address of the end point) < Maximum of column address AY (row address of start point) < EY (row address of the end point) < Maximum of row address column address
(X, Y) Start point row address
Window display area Fig 7
End point (X, Y) Whole DDRAM area
(8) Reverse display ON/OFF
The "Reverse display ON/OFF" function is used to reverse the display data without changing the contents of the DDRAM. Table 9
REV 0 1 Display Normal Reverse DDRAM data Display data 0 0 1 1 0 1 1 0
(9) Segment direction
The "Segment direction" function is used to reverse the assignments for the segment drivers and the column addresses, and it is possible to reduce restrictions for the placement of the LSI on LCD modules.
- 23 -
RAM Map 1 WLS HSW SEG0 SEG1 Palette C Palette A Palette A C0 A3 A2 A1 A0 B3 C0 C3 C2 C1 A3 A2 A1 A0 B3 B2 B1 B0 X=01H X=66H X=01H X=66H X=01H X=02H X=CCH X=02H X=CCH X=01H X=9BH X=99H X=CFH X=01H X=CFH X=00H X=9AH(L) X=03H X=CDH X=03H X=CDH X=02H X=9AH(H) X=CCH X=02H X=CCH X=02H X=99H X=01H(L) X=02H C3 C2 C1 B0 Palette B Palette C REF 256 Palette A A3 A2 A1 A0 B3 B2 B1 X=00H
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
SEG102 Palette B C3 B2 B1 B0 X=66H X=01H X=66H X=01H C2
SEG103
Mode Palette B
ABS
Palette C
Palette A
Palette B
Palette C
C1
C0
C3
C2
C1 X=CDH X=03H
SEG102 Palette B C3 C2 A0 B3 B2 B1 B0 X=66H X=01H
1 1 16bit 1 1 1 0 0 0 1 0 1 0 1 0 0 0 X=CEH 0 X=00H 0 0 1 1 0 X=CEH 0 0 1 1 x x 0 X=00H x 0 1 X=67H 0 1 0 0 0 8bit 0 0 0 x 0 X=00H
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
0 0 0 X=67H 0 x 1
x
0
X=67H
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
X=00H
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
X=67H
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X=00H
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X=CDH
X=CEH
X=CFH
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
X=03H
X=00H
X=01H
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
X=CEH
X=CFH
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X=00H
X=01H
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X=9AH
X=9BH
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X=00H
X=01H(H)
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
RAM Map 2 (256 Color Mode) HSW WLS SEG0 REF 256 Palette A A3 A2 A1 A0 B3 B2 Palette B C3 B1 B0 Palette C C2 C1 C0 A3 Palette A A2 A1 A0 B3 SEG1 Palette B C3 B2 B1 B0 Palette C C2 C1 C0 A3 Palette A A2 A1 Mode ABS
SEG103
Palette C
Palette A
Palette B
Palette C
C1
C0
C3
C2
C1 X=00H X=01H X=67H - D7 D6 D5 D4 D3 D2 D1 D0 X=66H - D7 D6 D5 D4 D3 D2 D1 D0 -
0 X X X 1 1 0 1 X 8bit 0
X=67H - D7 D6 D5 D4 D3 D2 D1 D0 - D7 D6 D5 D4 D3 D2 D1 D0
- D7 D6 D5 D4 D3 D2 D1 D0
-
-
-
- D7 D6 D5 D4 D3 D2 D1 D0
X=00H
- D7 D6 D5 D4 D3 D2 D1 D0
-
-
-
- D7 D6 D5 D4 D3 D2 D1 D0
SWAP
NJU6818
SWAP
REF
Palette A A3 A2 A1 A0 B3
Palette B C3 B2 B1 B0
Palette C C2 C1 C0
0 1 0 1 1 1 0
0
SEGAx SEGCx
SEGBx SEGBx
SEGCx SEGAx
Note1) In the 256-color mode, the vacant LSB bit is filled with "1". Note2) The function of 256-color mode is different from that of fixed 8-gradation mode (fixed 256-color mode). Note3) The written data in the DD RAM in "C256"=0 is not compatible with the data in "C256"=1. Note4) In the 256-color mode, only 8-bit length mode is available, but 16-bit is not.
C0
A3
A2
A1
A0
B3
B2
B1
B0
C0
A3
A2
A1
A0
B3
B2
B1
B0
- 24 -
HSW * * ABS REF SWAP 1 0 0 1 1 1 ABS REF SWAP 0 0 1 0 1 0 ABS REF SWAP 0 0 0 0 1 1
D11 SEGA0 D9 D8 D7 SEGB0 D5 D4 D3 D2 D1 D0 D1 SEGA0 D2 palette C D3 SEGC0 palette C D4 D7 D8 palette B D6 SEGB0 palette B D9 SEGB0 D10 palette B D12 D13 palette A SEGC0 SEGA0 D10 palette A palette A D14 D14 D13 D12 D10 D9 D8 D7 D4 D3 SEGC0 palette C D2 D1 D15 D15
HSW * *
HSW * *
HSW * *
ABS REF SWAP 1 0 1 1 1 0
D11
SEGC0
palette A
D10
D9
D8
D7
In the color mode and 16-bit data bus mode
X=00H X=67H
X=00H X=67H
X=00H X=67H
X=00H X=67H
SEGB0
palette B
D6
D5
D4
D3
D2
SEGA0
palette C
D1
D0
D11 SEGA103 D9 D8 D7 D6 palette A D10 SEGC103
D11
D15 palette A D14 D13 D12 D10 D9 SEGB103 palette B D8 D7 D4
D15 SEGA103 palette A D14 D13 D12 D10 D9
Column address / bit / segment assign
Column address / bit / segment assign
Column address / bit / segment assign
Column address / bit / segment assign
SEGC103
palette A
D10
D9
D8
D7
X=67H X=00H
X=67H X=00H
X=67H X=00H
X=67H X=00H
SEGB103 D5 D4 D3 SEGC103 palette C D2 D1 D0
palette B SEGB103
D6 palette B
D5
SEGB103
palette B
D8 D7 D4 SEGA103 palette C D3 D2 D1 SEGC103 palette C D3 D2 D1
(10) The relation among the DDRAM column address, display data, and segment drivers
D4
D3
NJU6818
SEGA103
palette C
D2
- 25 -
D1
D0
HSW 0 0
HSW 0 0
HSW 0 0
HSW 0 0
NJU6818
In the color mode and 8-bit data bus mode
- 26 ABS REF SWAP 1 0 0 1 1 1 ABS REF SWAP 0 0 1 0 1 0 ABS REF SWAP 0 0 0 0 1 1
D3 D7 D7 SEGA0 palette A D6 D5 D4 D2 SEGB0 palette B D1 D0 D7 D4 D3 SEGC0 palette C D2 D1
ABS REF SWAP 1 0 1 1 1 0
D2 D1 SEGC0 D5 palette A D6
D3
X=00H X=CEH
X=00H X=CEH
SEGC0
palette A SEGA0
D2 palette A
D1
X=00H X=CEH
X=00H X=CEH
D0 D7 SEGB0 D5 D4 D3 D2 D1 D0 D1 SEGA0 D2 palette C D3 SEGC0 palette C D4 D7 D0 palette B SEGB0 D6 palette B D1 D2
D0
D4
D7
SEGB0
palette B
D6
D5
D4
D3
D2
SEGA0
palette C
D1
D0
D3 SEGA103 D1 D0 D7 SEGB103 D5 D4 D3 SEGC103 palette C D2 D1 D0 palette B D6 palette A D2
D3
D7 SEGC103 palette A D6 D5 D4 D2 SEGB103 palette B D1 D0 D7
D7 SEGA103 palette A D6 D5 D4 D2 SEGB103 palette B D1 D0 D7
Column address / bit / segment assign X=01H X=CEH X=CFH X=00H
Column address / bit / segment assign X=01H X=CEH X=CFH X=00H
SEGC103
palette A
D2
D1
Column address / bit / segment assign X=01H X=CEH X=CFH X=00H
Column address / bit / segment assign X=01H X=CEH X=CFH X=00H
D0
D7
SEGB103
palette B
D6
D5
D4
X=CFH X=01H
X=CFH X=01H
D3
D4 SEGA103 palette C D3 D2 D1
D4
X=CFH X=01H
X=CFH X=01H
SEGA103
palette C
D2
D1
SEGC103
palette C
D3 D2 D1
D0
NJU6818
HSW ABS REF SWAP HSW ABS REF SWAP HSW ABS REF SWAP HSW ABS REF SWAP 1 * 1 1 D3 X=9AH SEGA 0 Palette A D2 D1 D0 D7 SEGB 0 Palette B D6 D5 X=9BH D4 D3 SEGC 0 Palette C D2 D1 D0 D7 SEGA 1 Palette A D6 D5 X=99H D4 D3 SEGB 1 Palette B D2 D1 D0 D7 X=9AH SEGC 1 Palette C D6 D5 D4 Column-address / bit / segment assign SEGC 1 Palette A SEGB 0 Palette B SEGC 0 Palette A D3 X=01H SEGA 102 Palette A D2 D1 D0 D7 SEGB 102 Palette B D6 D5 X=02H D4 D3 SEGC 102 Palette C D2 D1 D0 D7 SEGA 103 Palette A D6 D5 X=00H D4 D3 SEGB 103 Palette B D2 D1 D0 D7 X=01H SEGC 103 Palette C D6 D5 D4 SEGA 103 Palette C SEGC 103 Palette A SEGB 102 Palette B 1 * 1 0 D3 X=9AH X=9BH D2 D1 D0 D7 D6 D5 D4 D3 SEGA 0 Palette C D2 D1 D0 D7 D6 D5 X=99H D4 D3 SEGB 1 Palette B D2 D1 D0 D7 X=9AH SEGA 1 Palette C D6 D5 D4 Column-address / bit / segment assign SEGC 1 Palette A SEGB 0 Palette B SEGC 0 Palette A D3 X=01H SEGC 102 Palette A D2 D1 D0 D7 D6 D5 X=02H D4 D3 SEGA 102 Palette C D2 D1 D0 D7 D6 D5 X=00H D4 D3 SEGB 103 Palette B D2 D1 D0 D7 X=01H D6 D5 D4 SEGA 103 Palette C SEGC 103 Palette A SEGB 102 Palette B 1 * 0 1 D7 D6 D5 X=00H SEGB 0 Palette B D4 D3 D2 D1 D0 D7 SEGA 0 Palette C D6 D5 X=01H SEGA 1 Palette A SEGB 1 X=02H D4 D3 D2 D1 D0 D7 SEGB 1 Palette B D6 D5 D4 D3 SEGA 1 Palette C D2 D1 D0 Palette B SEGC 0 Palette C SEGA 0 Palette A D7 SEGC 102 Palette A D6 D5 X=99H D4 D3 D2 D1 D0 D7 SEGA 102 Palette C D6 D5 X=9AH SEGA 103 Palette A SEGB 103 X=9BH D4 D3 D2 D1 D0 D7 SEGB 103 Palette B D6 D5 D4 D3 D2 D1 D0 Palette B SEGC 102 Palette C 1 * 0 0 D7 D6 D5 X=00H X=01H X=02H D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 SEGC 1 Palette C D2 D1 D0 Column-address / bit / segment assign D7 SEGA 102 Palette A D6 D5 X=99H D4 D3 SEGB 102 Palette B D2 D1 D0 D7 D6 D5 X=9AH X=9BH D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 SEGC 103 Palette C D2 D1 D0
Column-address / bit / segment assign
- 27 -
NJU6818
In the color mode, 8-bit data bus mode, and C256 mode (C256=1)
HSW * * ABS REF SWAP * 0 0 * 1 1
D7 D6 D5
Column address / bit / segment assign X=00H X=67H
D4 D3 D2 D1 D0 D7 D6 D5
X=67H X=00H
D4 D3 D2 D1 D1 SEGA103 SEGC103 D2 palette C D0 D0
palette A
palette B
palette C
palette A
palette B
SEGA103
HSW * *
ABS REF SWAP * 0 1 * 1 0
D7 D6 D5
Column address / bit / segment assign X=00H X=67H
D4 D3 D2 D1 D0 D7 D6 D5
X=67H X=00H
D4 D3
palette A
palette B
palette C
palette A
SEGC103
- 28 -
SEGB103
SEGC0
SEGB0
SEGA0
palette B
SEGB103
SEGC0
SEGA0
SEGB0
palette C
HSW * *
HSW * *
HSW * * ABS REF SWAP 1 0 0 1 1 1 ABS REF SWAP 0 0 1 0 1 0 ABS REF SWAP 1 0 1 1 1 0
SEGC0 SEGA0 SEGA0 SEGB0
HSW * * ABS REF SWAP 0 0 0 0 1 1
SEGC0
In the B&W mode and 16-bit data bus mode
SEGB0
X=00H X=67H
X=00H X=67H
X=00H X=67H
SEGB0
X=00H X=67H
SEGB0
SEGA0
SEGC0
SEGA0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SEGC0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D14 D13 SEGA103 D12 D11 D10 D9 D8 SEGB103 D7 D6 D5 SEGC103 D4 D3 D2 D1 D0 SEGC103 D12 D11
D15
SEGC103
D15 D14 D13
SEGA103
D15 D14 D13 D12 D11 SEGB103 SEGB103 D9 D8 D12 D11 D10
Column address / bit / segment assign
Column address / bit / segment assign
Column address / bit / segment assign
Column address / bit / segment assign
X=67H X=00H
X=67H X=00H
X=67H X=00H
X=67H X=00H
SEGB103
D10 D9 D8 D7
D7 D6 D5 SEGA103 D4 D3 D2 D1 D0
D10 D9 D8 D7
SEGC103
SEGA103 D2 D1 D0
D6 D5 D4 D3
D6 D5 D4 D3 D2 D1 D0
NJU6818
- 29 -
NJU6818
In the B&W mode and 8-bit data bus mode
HSW 0 0 ABS REF SWAP 0 0 0 0 1 1
D7 D6
X=00H X=CEH
D5 D4 D2 D1 D0 D7
Column address / bit / segment assign X=01H X=CEH X=CFH X=00H
D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7
X=CFH X=01H
D4 D3 D2 D2 D1 D1 D1 D0 D0 D1
HSW 0 0
ABS REF SWAP 0 0 1 0 1 0
D7 D6
X=00H X=CEH
D5 D4 D2 D1 D0 D7
Column address / bit / segment assign X=01H X=CEH X=CFH X=00H
D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7
D4 D3 D3 SEGA103 SEGC103 SEGA103
SEGC103
SEGA103
SEGB103
SEGC0
SEGA0
SEGB0
X=CFH X=01H
D3 D2 D2
SEGC103
HSW 0 0
ABS REF SWAP 1 0 0 1 1 1
D3
X=00H X=CEH
D2 D1 D0 D7 D6 D5
Column address / bit / segment assign X=01H X=CEH X=CFH X=00H
D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D5
SEGB103
SEGC0
SEGB0
SEGA0
X=CFH X=01H
D4 D4
SEGA103
HSW 0 0
ABS REF SWAP 1 0 1 1 1 0
D3
X=00H X=CEH
D2 D1 D0 D7 D6 D5
Column address / bit / segment assign X=01H X=CEH X=CFH X=00H
D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6
SEGB103
SEGC0
SEGA0
SEGB0
X=CFH X=01H
SEGC103
- 30 -
SEGB103
SEGC0
SEGB0
SEGA0
NJU6818
HSW ABS REF SWAP HSW ABS REF SWAP HSW ABS REF SWAP HSW ABS REF SWAP 1 * 1 1 1 * 1 0 1 * 0 1 1 * 0 0
SEGA 0
D3 X=9AH D2 D1 D0
SEGC 0
D3 X=9AH D2 D1 D0
SEGC 0
D7 D6 D5 X=00H D4
SEGA 0
D7 D6 D5 X=00H D4
SEGB 0
D7 D6 D5 X=9BH D4
SEGB 0
D7 D6 D5 X=9BH D4
SEGB 0
D3 D2 D1 D0
SEGB 0
D3 D2 D1 D0
SEGC 0
D3 D2 D1 D0
SEGA 0
D3 D2 D1 D0
SEGA 0
D7 D6 D5 X=01H D4
SEGC 0
D7 D6 D5 X=01H D4
SEGA 1
D7 D6 D5 X=99H D4
SEGC 1
D7 D6 D5 X=99H D4
SEGC 1
D3 D2 D1 D0
SEGA 1
D3 D2 D1 D0
SEGB 1
D3 D2 D1 D0
SEGB 1
D3 D2 D1 D0
SEGB 1
D7 D6 D5 X=02H D4
SEGB 1
D7 D6 D5 X=02H D4
SEGC 1
D7 X=9AH X=01H X=02H X=00H X=01H D6 D5 D4
SEGA 1
D7 X=9AH D6 D5 D4
SEGA 1
D3 D2 D1 D0
SEGC 1
D3 D2 D1 D0
Column-address / bit / segment assign
Column-address / bit / segment assign
Column-address / bit / segment assign
Column-address / bit / segment assign
SEGA 102 D3 D2 D1 D0 SEGB 102 D7 D6 D5 D4 SEGC 102 D3 D2 D1 D0 SEGA 103 D7 D6 D5 D4 SEGB 103 D3 D2 D1 D0 SEGC 103 D7 D6 D5 D4
SEGC 102 D3 X=01H X=02H X=00H X=01H D2 D1 D0 SEGB 102 D7 D6 D5 D4 SEGA 102 D3 D2 D1 D0 SEGC 103 D7 D6 D5 D4 SEGB 103 D3 D2 D1 D0 SEGA 103 D7 D6 D5 D4
SEGC 102 D7 D6 D5 X=99H X=9AH X=9BH D4 SEGB 102 D3 D2 D1 D0 SEGA 102 D7 D6 D5 D4 SEGC 103 D3 D2 D1 D0 SEGB 103 D7 D6 D5 D4 SEGA 103 D3 D2 D1 D0
SEGA 102 D7 D6 D5 X=99H X=9AH X=9BH D4 SEGB 102 D3 D2 D1 D0 SEGC 102 D7 D6 D5 D4 SEGA 103 D3 D2 D1 D0 SEGB 103 D7 D6 D5 D4 SEGC 103 D3 D2 D1 D0
- 31 -
NJU6818
Bit assignments between write and read data (In the 16-bit data bus mode) ABS=0
Write data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Read data
D15
D14
D13
D12
*
D10
D9
D8
D7
*
*
D4
D3
D2
D1
*
ABS=1
Write data D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Read data
*
*
*
*
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Examples of write and read data (In the 8 bit bus mode) ABS=0, HSW=0, C256=0 (Address; 00, 02......CC,CEH)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
D7
D6
D5
D4
*
D2
D1
D0
ABS=0, HSW=0, C256=0 (Address; 01,03H......CD,CFH)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
D7
*
*
D4
D3
D2
D1
1
ABS=1, HSW=0, C256=0 (Address; 00, 02......CC,CEH)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
*
*
*
*
D3
D2
D1
D0
ABS=1, HSW=0, C256=0 (Address; 01,03H...... CD,CFH)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
D7
D6
D5
D4
D3
D2
D1
D0
ABS=0, HSW=1, C256=0 (Address; 00, 01......9A,9BH)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
D7
D6
D5
D4
D3
D2
D1
D0
ABS=0, HSW=0, C256=1 (Address; 00, 01...... 66 ,67H)
Write data D7 D6 D5 D4 D3 D2 D1 D0
Read data
D7
D6
D5
D4
D3
D2
D1
D0
*: Invalid Data
- 32 -
NJU6818
(11) Gradation palette
In the gradation mode, either variable or fixed gradation mode is selected by programming the "PWM" register of the "Gradation control" instruction. PWM=0: PWM=1: Variable gradation mode (Select 16-gradation level out of 32-gradation level of the gradation palette) Fixed gradation mode (Fixed 8-gradation level)
In these modes, each of the gradation palettes of the Aj, Bj and Cj can select 16-gradation level out of 32gradation level by setting 5-bit data to the "PA" registers in the "Gradation palette j" instructions (j=0 to Fh). For instance, the gradation palettes Aj correspond to the SEGAi, the Bj to the SEGBj, and the Cj to the SEGCi (j=0 to 15, i=0 to 103).
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NJU6818
Correspondence between display data and gradation palettes Table 10 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
(MSB) Display data (LSB) 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Gradation palette Palette 0 Palette 1 Palette 2 Palette 3 Palette 4 Palette 5 Palette 6 Palette 7 Palette 8 Palette 9 Palette10 Palette11 Palette12 Palette13 Palette14 Palette15 Default palette value 00000 00011 00101 00111 01001 01011 01101 01111 10001 10011 10101 10111 11001 11011 11101 11111
Gradation palette table
(Variable gradation mode, PWM="0", MON="0")
Table 11 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
Palette value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Gradation level 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 Gradation palette Palette 0(default) Palette 1(default) Palette 2(default) Palette 3(default) Palette 4(default) Palette 5(default) Palette 6(default) Palette 7(default) Palette value 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Gradation level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Gradation palette Palette 8(default) Palette 9(default) Palette 10(default) Palette 11(default) Palette 12(default) Palette 13(default) Palette 14(default) Palette 15(default)
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NJU6818
Gradation palette table (Fixed gradation mode, PWM="1", MON="0") Table 12 8-gradation segment drivers
(MSB) Display data (LSB) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 * * * * * * * * Gradation level 0/7 1/7 2/7 3/7 4/7 5/7 6/7 7/7 (MSB) Display data (LSB) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 * * * * * * * * * * * * * * * * Gradation level 0/7 3/7 5/7 7/7
Correspondence between display data and gradation level (B&W mode, MON="1") Table 13
(MSB) Display data (LSB) 0 1 * * * * * * Gradation level 0 1
*:Don't care
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NJU6818
(12) Gradation control and display data
(12-1) Gradation mode In the graduation mode, each pixel for RGB corresponds to successive 3 segment-drivers, and each segment driver provides 16-gradation PWM output by controlling 4-bit display data of the DDRAM. Accordingly, the LSI can drive up to 104x80 pixels in 4096-color (16-gradation x 16-gradation x 16-gradation = 4-bit x 4-bit x 4-bit). In addition, the LSI can transfer the display data for the RGB by 16-bit at once or 8-bit two times. The data assignment between gradation palettes and segment drivers varies in accordance with setting for the "SWAP" and "REF" registers of the "Display control (2)" instruction.
(REF, SWAP)=(0, 0) or (1, 1)
SEGAi SEGBi SEGCi (i=0 to 103)
Palette Aj Paltte Aj
PaletteBj
PaletteCj
Gradation palette j=0 to 15 Gradation control circuit
0 1 MSB
0 1
0 1
0 1 0 1 LSB MSB
0
0
1 0 1 0 LSB MSB
1 0
1 0
1 0 LSB
Display data in DDRAM
0 D7 ABS=1 (D 3
HSW=1 (D 7 C256=1 (D
7
0 D6 D2 D6 D6
0 D5 D1 D5 D5
0 D4 D0 D4 *
0 D2 D7 D3 D4
0 D1 D6 D2 D3
0 D0 D5 D1 D2
1 D7 D4 D0 *
1 D4 D3 D7 D1
1 D3 D2 D6 D0
1 D2 D1 D5 *
1 D1 D0) D4) *)
Display data from MPU
Column address:2nH :2n+1H
Note) DDRAM column address :2nH ,2nH+1H :CEH -2nH , CFH-(2nH+1H) HSW=1; 00H to 9BH C256=1; 00H to 67H
(REF="0") (REF="1")
(REF, SWAP)=(0, 1) or (1, 0)
SEGAi SEGBi SEGCi (i=0 to 103)
PaletteAj
Palette Bj
PaletteCj
Gradation palette j=0 to 15 Gradation control circuit
1 LSB
1
1
1 1 MSB LSB
0
0
0 0 MSB LSB
0
0
0 Display data in DDRAM MSB
0 D7 ABS=1 (D 3 HSW=1 (D 7 C256=1 (D 7
0 D6 D2 D6 D6
0 D5 D1 D5 D5
0 D4 D0 D4 *
0 D2 D7 D3 D4
0 D1 D6 D2 D3
0 D0 D5 D1 D2
1 D7 D4 D0 *
1 D4 D3 D7 D1
1 D3 D2 D6 D0
1 D2 D1 D5 *
1 D1 D0) D4) *)
Display data from MPU
Column address:2nH :2n+1H
Note) DDRAM column address : 2nH ,2nH+1H : CEH -2nH , CFH-(2nH+1H) HSW=1; 00H to 9BH C256=1; 00H to 67H
(REF="0") (REF="1")
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NJU6818
In the 16-bit data bus mode, the data assignments between the gradation palettes and the segment drivers vary in accordance with setting for the "SWAP" and "REF" bits of the "Display control (2)" instruction as well as the assignment in the 8-bit data bus mode. (REF, SWAP)=(0, 0) or (1, 1)
SEGAi SEGBi SEGCi (i=0 to 103)
PaletteAj
Palette Bj
PaletteCj
Gradation palette j=0 to 15 Gradation control circuit
0 MSB 0 D15
ABS=1
0
0
0 0 LSB MSB 0 D12 D8 0 D10 D7
0
0
1 1 LSB MSB 1 D7 D4 1 D4 D3
1
1
1 LSB 1 D1 D0)
Display data in DDRAM
0 D14
0 D13 D9
0 D9 D6
0 D8 D5
1 D3 D2
1 D2 D1
Display data from MPU ; Column address nH
(D11 D10
Note) DDRAM column address :nH (REF="0") :67H - nH (REF="1")
(REF, SWAP)=(0, 1) or (1, 0)
SEGAi SEGBi SEGCi i=0 to 103
PaletteAj
Palette Bj
PaletteCj
Gradation palette j=0 to 15 Gradation control circuit
1 LSB
1
1
1
1
0
0
0
0
0
0
0 MSB
Display data in DDRAM
MSB LSB
MSB LSB
0 D15
0 D14
0 D13 D9
0 D12 D8
0 D10 D7
0 D9 D6
0 D8 D5
1 D7 D4
1 D4 D3
1 D3 D2
1 D2 D1
1 D1 D0)
Display data from MPU
Column address; nH
ABS=1 (D11 D10
Note) DDRAM column address :nH :67H -nH
(REF="0") (REF="1")
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NJU6818
(12-2) B&W mode (MON="1") In the B&W mode, 3 bits of the MSB data are used in both of the 16-bit and 8-bit data bus modes. In the 16-bit data bus mode (Similarly 8-bit data bus access) (REF, SWAP)=(0, 0) or (1, 1)
SEGAi SEGBi SEGCi (i=0 to 103)
PaletteAj
Palette Bj
Palette Cj
Gradation palette j=0 to 15 Gradation control circuit
0 MSB 0 D15
ABS=1 (D11
0
0
0
0
0
0
1
1
1
1
1 LSB
Display data in DDRAM
LSB MSB 0 D14 D10 0 D13 D9 0 D12 D8 0 D10 D7 0 D9 D6 0 D8 D5
LSB MSB 1 D7 D4 1 D4 D3 1 D3 D2 1 D2 D1
1 D1 D0)
Display data in DDRAM
Column address; nH
Note) DDRAM column address : nH : 67H-nH
(REF="0") (REF="1")
(REF, SWAP)=(0, 1) or (1, 0)
SEGAi SEGBi SEGCi (i=0 to 103)
PaletteAj
PaletteBj
PaletteCj
Gradation palette j=0 to 15 Gradation control circuit
1 LSB
1
1
1 1 MSB LSB
0
0
0 0 MSB LSB
0
0
Display data in DDRAM 0 MSB
0 D15
ABS=1
0 D14
0 D13 D9
0 D12 D8
0 D10 D7
0 D9 D6
0 D8 D5
1 D7 D4 4
1 D4 D3
1 D3 D2
1 D2 D1
1 D1 D0)
Display data in DDRAM
Column address; nH
(D11 D10
Note ) DDRAM column address: nH : 67H-nH
(REF="0") (REF="1")
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NJU6818
(13) Display timing generator
The display-timing generator creates the timing pulses such as the CL, the FLM, the FR and the CLK by dividing the oscillation frequency oscillate an external or internal resister mode. The each of timing pulses is outputted through the each output terminals by "SON"=1.
(14) LCD line clock (CL)
The LCD line clock (CL) is used as a count-up signal for the line counter and a latch signal for the data latch circuit. At the rising edge of the CL signal, the line counter is counted-up and 312-bit display data, corresponding to this line address, is latched into the data latch circuit. And at the falling edge of the CL signal, this latched data output on the segment drivers. Read out timing of the display data, from DDRAM to the latch circuits, is completely independent of the access timing to MPU. For this reason, the MPU can access to the LSI regardless of an internal operation.
(15) LCD alternate signal (FR) and LCD synchronous signal (FLM)
The FR and FLM signals are created from the CL signal. The FR signal is used to alternate the crystal polarization on a LCD panel. It is programmed that the FR signal is toggle on every frame in the default setting or once every N lines in the N-line inversion mode. The FLM signal is used to indicate a start line of a new display frame. It presets an initial display line address of the line counter when the FLM signal becomes "1".
(16) Data latch circuit
The data latch circuit is used to temporarily store the display data that will output on the segment drivers. The display data in this circuit is updated in synchronization of the CL signal. The "All pixels ON/OFF", "Display ON/OFF" and "Reverse display ON/OFF" instructions change the display data in this circuit but do not change the display data of the DDRAM.
(17) Common and segment drivers
The LSI includes 312-segment drivers and 80-common drivers. The common drivers generate LCD driving waveforms composed of the VLCD, V1, V4 and VSS in accordance with the FR signal and scanning data. The segment drivers generate waveforms composed of the VLCD, V2, V3 and VSS in accordance with the FR signal and display data.
(18) Chip Identification (ID)
The NJU6818 can read ID data, which is determined by fixing ID3, ID2, ID1 and ID0 pins to "1" (VDD) or "0" (VSS). When the parallel interface is used, the ID data can be read out through the D7, D6, D5 and D4 pins as upper 4-bit data of the internal register. When the serial interface is used, the ID data can be read out as follows. In the 4-line serial interface mode, "ID read-out instruction" must be set by IDR=1 during the SDA and SCL pins are enabled by CS=1. First, the serial data on the SDA must be input at the rising edge of the SCL clock, next the th th SDA must be in high-impedance (Hi-Z) at the falling edge of the 8 SCL clock. From the rising edge of the 9 SCL clock, the ID data such as ID3, ID2, ID1 and ID0 is read out. The serial data after the ID0 is undefined, and this th reading mode is returned to the writing mode at the rising edge of the 16 SCL clock. The serial data on the SDA th th at the 8 and 16 SCL clocks applies specified serial interface timing. In the 3-line serial interface mode, the SDA must be in high-impedance (Hi-Z) at the falling edge of the 9 SCL th clock. From the rising edge of the 10 SCL clock, the ID data is read out as well as operation in the 4-line serial interface mode. The serial data after ID0 is undefined, and this reading mode is returned to the writing mode at the th th th rising edge of the 18 SCL clock. The serial data on the SDA at the 9 and 18 SCL clocks applies specified serial interface timing. Note) Refer to the "Serial Interface Timing" for the detail
th
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NJU6818
ID Read in the 4-Line serial interface mode CSb RS SDA SCL 1 2 8 9 10 11 12 15 16 D7 D6 VALID D0
Hi-z
ID3
ID2
ID1
ID0
unfixed
unfixed
ID Read in the 4-Line serial interface mode CSb SDA SCL 1 2 9 10 11 12 13 17 18 RS D7 D0
Hi-z
ID3
ID2
ID1
ID0
unfixed
unfixed
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NJU6818
LCD Driving waveforms (In the B&W mode, Reverse display OFF, 1/81 duty)
COM0 COM1 CL
81
1
2345
81
1
2345
81 1
SEG0
SEG1
SEG2
FLM
FR VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS
COM0
COM1
SEG0
SEG1
Fig 8
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NJU6818
(19) Oscillator
The oscillator generates internal clocks for the display timing and the voltage booster. Since the LSI has internal capacitor (C) and resistor (R) for the oscillation, external capacitor and resistor are not usually required. However, in case that an external resistor is used, the resister is connected between the OSC1 and OSC2 terminals. The external resistor becomes enabled by setting "1" to the "CKS" register of "Data bus length" instruction. When the internal oscillator is not used, the external clocks with 50% duty cycle ratio must be input to the OSC1 terminal. In addition, the feed back resister for the oscillation is varied by programming the "Rf" register of the "Frequency control" instruction, so that it is possible to optimize the frame frequency for a LCD panel. Setting examples of the MON (B&W /Gradation) and the PWM (Variable gradation /Fixed gradation) are described, as follows.
(19-1) Internal oscillation mode (CKS=0)
Symbol FR1 FR2 FR3 MON 0 0 1 PWM 0 1 * Display mode Variable gradation mode Fixed gradation mode B&W mode
*: Don't care
(19-2) External resistor oscillation mode (CKS=1) The internal clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the "MON" and "PWM" registers must be set as well.
(19-3) External clock input mode (CKS=1) The external clocks must be adjusted to the same frequency as the one in using the internal oscillation mode, and the "MON" and "PWM" registers must be set as well.
(20) Power supply circuits
The internal power supply circuits are composed of the voltage booster, the electrical variable resister (EVR), the voltage regulator, reference voltage generator and the voltage followers. The condition of the power supply circuits is arranged by programming the "DCON" and "AMPON" registers on the "Power control" instruction. For this arrangement, some parts of the internal power supply circuits are activated in using an external power supply, as shown in the following table. Table 15
DCON 0 0 1 AMPON 0 1 1 Voltage booster Disable Disable Enable Voltage followers Voltage regulator EVR Disable Enable Enable External voltage VOUT, VLCD, V1, V2, V3, V4 VOUT -
+ +
Note 1, 3 2, 3 -
+ -
Note1) The internal power circuits are not used. The external VOUT is required and the C1 , C1 , C2 , C2 , C3 , C3 , + + C4 , C4 , C5 , C5 , VREF, VREG and VEE terminals must be open. Note2) The internal power circuits except the voltage booster are used. The external VOUT is required and the C1 , + + + + C1 , C2 , C2 , C3 , C3 , C4 , C4 , C5 , C5 and VEE terminals must be open. The reference voltage is required to VREF terminal. Note3) The relation among the voltages should be maintained as follows. VOUT VLCD V1 V2 V3 V4 VSS
+
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NJU6818
(21) Voltage booster
The voltage booster generates maximum 6x voltage of the VEE level. It is programmed so that the boost level is selected out of 1x, 2x, 3x, 4x, 5x and 6x by the "Boost level select" instruction. The boosted voltage VOUT must not exceed beyond the value of 18.0V, otherwise the voltage stress may cause a permanent damage to the LSI. Boosted voltages VOUT=18V VOUT=9.9V
VEE=3.3V VSS=0V 3-time boost Capacitor connections for the voltage Booster 6-time boost
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
VEE=3V VSS=0V 6-time boost
5-time boost + + + + + +
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
+ + + +
+
4-time boost
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
3-time boost + + +
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
2-time boost + +
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5VOUT VSS
+
+
+
+
Fig 9
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NJU6818
(22) Reference voltage generator
The reference voltage generator is used to produce the reference voltage (VBA), which is output from the VBA terminal and should be input to the VREF terminal. VBA = VEE x 0.9
(23) Voltage regulator
The voltage regulator, composed of a gain control circuit and an operational amplifier, and is used to gain the reference voltage (VREF) and to create the regulated voltage (VREG). The VREG is used as an input voltage to the EVR circuits which is programmed by the "VU" register of the "Boost level" instruction. VREG = VREF x N (N: register value for the boost level)
(24) Electrical variable resister (EVR)
The EVR is variable within 128-step, and is used to fine-tune the LCD driving voltage (VLCD) by programming the "DV" register of the "EVR control" instruction, so that it is possible to optimize the contrast level of LCD panels. VLCD = 0.5 x VREG + M (VREG - 0.5 x VREG) / 127 (M: register value for the EVR)
(25) LCD driving voltage generation circuit
LCD driving voltage generation circuit generates the VLCD voltage levels as VLCD, V1, V2, V3 and V4 with internal E.V.R and the bleeder resistors. The bias ratio of the LCD driving voltage is selected out of 1/4, 1/5, 1/6, 1/7, 1/8, 1/9 and 1/10. In using the internal power supply, the capacitors CA2 must be connected to the VLCD, V1, V2, V3 and V4 terminals, and the CA2 value must be determined by the evaluation with actual LCD modules. In using the external power supply, the external LCD driving voltages such as the VLCD, V1, V2, V3 and V4 are supplied and the internal power supply circuits must be set to "OFF" by DCON = AMPON = "0". In this mode, voltage booster terminals such as C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, VEE, VREF and VREG must be opened. In case that the voltage booster is not used but only some parts of internal power supply circuits (Voltage followers, Voltage regulator and EVR) are used, the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+ and C5- terminals must be opened. And, the external power supply is input to the VOUT terminal, and the reference voltage to the VREF terminal. The capacitor CA3 must connect to the VREG terminal for voltage stabilization.
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NJU6818
Connections of the capacitors for voltage booster
Using all of the internal power supply circuits (6-time boost) VDD VDD VEE VBA CA3 VSS CA3 VSS CA1 CA1 CA1 CA1 CA1 VREF VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
Using only external power supply circuits VDD
VDD VEE VBA VREF VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
NJU6818
NJU6818
CA1 VSS CA2 CA2 CA2 CA2 VSS CA2
VOUT
VOUT
VLCD V1 V2 V3 V4 Fig 10
VLCD V1 External Power V2 circuit V3 V4
VLCD V1 V2 V3 V4 Fig11
Reference values
CA1 CA2 CA3 1.0 to 4.7uF 1.0 to 2.2uF 0.1uF
Note) B grade capacitors are required.
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NJU6818
Using internal power supply circuits without the reference voltage generator (1) (6-time boost) VDD VDD VEE VBA VREF CA3 VSS CA1 CA1 CA1 CA1 CA1 VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
Thermistor
Using internal power supply circuits without the reference voltage generator (2) (6-time boost) VDD VDD VEE VBA VREF CA3 VSS CA1 CA1 CA1 CA1 CA1 VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
NJU6818
NJU6818
CA1 VSS CA2 CA2 CA2 CA2 VSS CA2
VOUT
CA1 VSS CA2 CA2 CA2 CA2 VSS Fig 12 CA2
VOUT
VLCD V1 V2 V3 V4
VLCD V1 V2 V3 V4 Fig 13
Reference value
CA1 CA2 CA3 1.0 to 4.7F 1.0 to 2.2F 0.1F
Note) B grade capacitors are required.
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NJU6818
Using internal power supply circuits without the voltage booster
VDD
VDD VEE VBA
CA3 CA3 VSS
VREF VREG C 1C 1+ C 2C 2+ C 3C 3+ C 4C 4+ C 5C 5+
VSS
NJU6818
External power circuit
VOUT
CA2 CA2 CA2 CA2 VSS CA2
VLCD V1 V2 V3 V4 Fig 14
Reference value
CA1 CA2 CA3 1.0 to 4.7F 1.0 to 2.2F 0.1F
Note) B grade capacitors are required.
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NJU6818
(26) Partial display function
The partial display function is used to partially specify some parts of display area on LCD panels. By using this function, LCD modules can work in lower duty cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage. It is usually used to display a time and calendar, and is also used to optimize the LSI condition in accordance with the display size. It can be programmed to select the duty cycle ratio (1/13, 1/17, 1/27, 1/33, 1/39,1/47, 1/57,1/69,1/77,1/81 in "DSE" is "0"), the LCD bias ratio, the boost level and the EVR value by the instructions.
Partial display image NJRC LCD DRIVER Low Power and Low Voltage Normal display Partial display sequence Optional status
LCD DRIVER
Partial display
Display OFF (ON/OFF="0")
Internal Power supply OFF (DCON="0", AMPON="0")
WAIT
Setting for LCD driving voltage-related functions
- Boost level - EVR value - LCD bias ratio
Internal Power supply ON (DCON="1", AMPON="1")
WAIT Setting for display-related functions - Duty cycle ratio - Initial display line - Initial COM line - Other instructions
Display ON (ON/OFF ="1")
Partial display Status
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NJU6818
(27) Discharge circuit
Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and the VLCD terminals. This circuit is activated by setting "0" to the "DIS" register of the "Discharge" instruction or by setting the "RESb" terminal to "0" level. The "Discharge ON/OFF" instruction is usually required just after the internal power supply is turned off by setting "0" into the "DCON" and "AMPON" registers, or just after the external power supply is turned off. During the discharge operation, the internal or external power supply must not be turned on.
(28) Reset circuit
The reset circuit initializes the LSI into the following default status. It is activated by setting the RESb terminal to "0". The RESb terminal is usually required to connect to MPU reset terminal in order that the LSI can be initialized at the same timing of the MPU. Default status 1. DDRAM display data 2. Column address 3. Row address 4. Initial display line 5. Display ON/OFF 6. Reverse display ON/OFF 7. Duty cycle ratio 8. N-line Inversion ON/OFF 9. COM scan direction 10. Increment mode 11. Reverse SEG direction 12. SWAP mode 13. EVR value 14. Internal power supply 15. Display mode 16. LCD bias ratio 17. Gradation Palette 0 18. Gradation Palette 1 19. Gradation Palette 2 20. Gradation Palette 3 21. Gradation Palette 4 22. Gradation Palette 5 23. Gradation Palette 6 24. Gradation Palette 7 25. Gradation Palette 8 26. Gradation Palette 9 27. Gradation Palette 10 28. Gradation Palette 11 29. Gradation Palette 12 30. Gradation Palette 13 31. Gradation Palette 14 32. Gradation Palette 15 33. Gradation mode control 34. Data bus length 35. Discharge circuit :Undefined :(00)H :(00)H :(0)H (1st line) :OFF :OFF (normal) :1/81 duty(DSE=0) :OFF :COM0 COM79 :OFF :OFF (normal) :OFF (normal) :(0, 0, 0, 0, 0, 0, 0) :OFF :Gradation display mode :1/9 bias :(0, 0, 0, 0, 0) :(0, 0, 0, 1, 1) :(0, 0, 1, 0, 1) :(0, 0, 1, 1, 1) :(0, 1, 0, 0, 1) :(0, 1, 0, 1, 1) :(0, 1, 1, 0, 1) :(0, 1, 1, 1, 1) :(1, 0, 0, 0, 1) :(1, 0, 0, 1, 1) :(1, 0, 1, 0, 1) :(1, 0, 1, 1, 1) :(1, 1, 0, 0, 1) :(1, 1, 0, 1, 1) :(1, 1, 1, 0, 1) :(1, 1, 1, 1, 1) :Variable gradation mode :8-bit data bus length :(DIS/DIS2) : "0"
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NJU6818
(29) Power supply ON/OFF sequences
The following paragraphs describe power supply ON/OFF sequences, which are to protect the LSI from over current. (29-1) Using an external power supply Power supply ON sequence Logic voltage (VDD) must be always input first, and next the LCD driving voltages (V1 to V4 and VLCD) are turned on. In using the external VOUT, the VDD must be input first, next the reset operation must be performed, and finally the VOUT can be input Power supply OFF sequence Either the reset operation, cutting off the V1 to V4 and VLCD from the LSI, by the RESb terminal or the "Power control" instruction must be performed first, and next the VDD is turned off. It is recommended that a series-resister between 50 and 100 is added on the VLCD line (or VOUT line in using only the external VOUT voltage) in order to protect the LSI from the over current.
(29-2) Using the internal power supply circuits
Power supply ON sequence The VDD must be input first, next the reset operation must be performed, and finally the V1 to V4 and the VLCD can be turned on by setting "1" to the "DCON" and "AMPON" registers of the "Power control" instruction. Power supply OFF sequence Either the reset operation by the RESb terminal or the "Power control" instruction must be performed first, and next the input voltage for the voltage booster (VEE) and the VDD can be turned off. If the VEE is supplied from different power sources for the VDD, the VEE is turned off first and next the VDD is turned off
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NJU6818
(30) Referential instruction sequences (30-1) Initialization in using the internal power supply circuits
VDD, VEE power ON
Wait for power-ON stabilization
RESET Input WAIT
Setting for LCD driving voltage-related functions
- EVR value - LCD bias ratio - Power control (DCON="1", AMPON="1")
End of initialization
(30-2) Display data writing
End of Initialization
Setting for display-related functions
- Initial display line - Increment mode - Column address - Row address
Display data write
Display ON (ON/OFF ="1")
- 51 -
NJU6818
(30-3) Power OFF
Optional status
Power save or reset operation
- All COM/SEG output VSS level.
Discharge ON
WAIT
VEE, VDD power OFF
- 52 -
NJU6818
(31) Instruction table
Instruction Table (1)
Instructions
CSb
Code (80 series MPU I/F)
RS RDb WRb RE2 RE1 RE0
Code D7 D6 D5 D4 D3 D2 D1 D0
Functions
Display data write
0
0
1
0
0/1 0/1 0/1
Write Data
Write display data to DDRAM
Display data read Column address (Lower) [0H] Column address (Upper) [1H] Row address (Lower) [2H] Row address (Upper) [3H] Initial display line (Lower) [4H] Initial display line (Upper) [5H] N-line inversion (Lower) [6H] N-line inversion (Upper) [7H] Display control (1) [8H] Display control (2) [9H] Increment control [AH] Power control [BH] Duty cycle ratio [CH] Boost level / ID read [DH] LCD bias ratio [EH] RE register [FH]
0
0
0
1
0/1 0/1 0/1
Read Data
Read display data from DDRAM
0
1
1
0
0
0
0
0
0
0
0
AX3
AX2
AX1
AX0
DDRAM column address
0
1
1
0
0
0
0
0
0
0
1
AX7
AX6
AX5
AX4
DDRAM column address
0
1
1
0
0
0
0
0
0
1
0
AY3
AY2
AY1
AY0
DDRAM row address
0
1
1
0
0
0
0
0
0
1
1
*
AY6
AY5
AY4
DDRAM row address Row address for an initial COM line (Scan start line) Row address for an initial COM line (Scan start line) The number of N-line inversion
0
1
1
0
0
0
0
0
1
0
0
LA3
LA2
LA1
LA0
0
1
1
0
0
0
0
0
1
0
1
*
LA6
LA5
LA4
0
1
1
0
0
0
0
0
1
1
0
N3
N2
N1
N0
0
1
1
0
0
0
0
0
1
1
1
*
N6
N5
N4
The number of N-line inversion
SHIFT: Common direction
0
1
1
0
0
0
0
1
0
0
0
SHIFT MON
ALL ON
ON/ MON: Gradation or B/W display mode OFF ALLON: All pixels ON/OFF
0
1
1
0
0
0
0
1
0
0
1
REV
0
1
1
0
0
0
0
1
0
1
0
WIN
0
1
1
0
0
0
0
1
0
1
1
AMP ON
ON/OFF: Display ON/OFF REV: Reverse display ON/OFF NLIN: N-line inversion ON/OFF, NLIN SWAP REF SWAP: SWAP mode ON/OFF REF: Segment direction WIN: Window addressing mode ON/OFF AIM: Read-modify-write ON/OFF AIM AYI AXI AYI: Row auto-increment mode ON/OFF AXI: Column auto-increment mode ON/OFF AMPON: Voltage followers ON/OFF HALT: Power save ON/OFF DC HALT ACL ON DCON: Voltage booster ON/OFF ACL: Reset
DS2 DS1 DS0
0
1
1
0
0
0
0
1
1
0
0
DS3
Set LCD duty cycle ratio Set boost level Sets ID reading interface Sets LCD bias ratio
0
1
1
0
0
0
0
1
1
0
1
IDR
VU2
VU1
VU0
in
the
serial
0
1
1
0
0
0
0
1
1
1
0
*
B2
B1
B0
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0
RE2
RE1
RE0 RE flag set
Note 1) Note 2) Note 3)
* : Don't care. [ NH] : Address of instruction register The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
- 53 -
NJU6818
Instruction Table (2)
Instructions
CSb
Code (80 series MPU I/F)
RS RDb WRb RE2 RE1 RE0
Code D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0
Functions Sets palette values to gradation palette A0(PS=0)/A8(PS=1) Sets palette values to gradation palette A0(PS=0)/A8(PS=1) Sets palette values to gradation palette A1(PS=0)/A9(PS=1) Sets palette values to gradation palette A1(PS=0)/A9(PS=1) Sets palette values to gradation palette A2(PS=0)/A10(PS=1) Sets palette values to gradation palette A2(PS=0)/A10(PS=1) Sets palette values to gradation palette A3(PS=0)/A11(PS=1) Sets palette values to gradation palette A3(PS=0)/A11(PS=1) Sets palette values to gradation palette A4(PS=0)/A12(PS=1) Sets palette values to gradation palette A4(PS=0)/A12(PS=1) Sets palette values to gradation palette A5(PS=0)/A13(PS=1) Sets palette values to gradation palette A5(PS=0)/A13(PS=1) Sets palette values to gradation palette A6(PS=0)/A14(PS=1) Sets palette values to gradation palette A6(PS=0)/A14(PS=1)
Gradation palette A0/A8 (Lower) [0H] Gradation palette A0/A8 (Upper) [1H] Gradation palette A1/A9 (Lower) [2H] Gradation palette A1/A9 (Upper) [3H] Gradation palette A2/A10 (Lower) [4H] Gradation palette A2/A10 (Upper) [5H] Gradation palette A3/A11 (Lower) [6H] Gradation palette A3/A11 (Upper) [7H] Gradation palette A4/A12 (Lower) [8H] Gradation palette A4/A12 (Upper) [9H] Gradation palette A5/A13 (Lower) [AH] Gradation palette A5/A13 (Upper) [BH] Gradation palette A6/A14 (Lower) [CH] Gradation palette A6/A14 (Upper) [DH] RE register [FH]
0
1
1
0
0
0
1
PA03/ PA02/ PA01/ PA00/ PA83 PA82 PA81 PA80
0
1
1
0
0
0
1
0
0
0
1
*
*
*
PA11/ PA91
PA04/ PA84
0
1
1
0
0
0
1
0
0
1
0
PA13/ PA12/ PA93 PA92
PA10/ PA90
0
1
1
0
0
0
1
0
0
1
1
*
*
*
PA14/ PA94
0
1
1
0
0
0
1
0
1
0
0
PA23/ PA22/ PA21/ PA20/ PA103 PA102 PA101 PA100
0
1
1
0
0
0
1
0
1
0
1
*
*
*
PA24/ PA104
0
1
1
0
0
0
1
0
1
1
0
PA33/ PA32/ PA31/ PA30/ PA113 PA112 PA111 PA110
0
1
1
0
0
0
1
0
1
1
1
*
*
*
PA34/ PA114
0
1
1
0
0
0
1
1
0
0
0
PA43/ PA42/ PA41/ PA40/ PA123 PA122 PA121 PA120
0
1
1
0
0
0
1
1
0
0
1
*
*
*
PA44/ PA124
0
1
1
0
0
0
1
1
0
1
0
PA53/ PA52/ PA51/ PA50/ PA133 PA132 PA131 PA130
0
1
1
0
0
0
1
1
0
1
1
*
*
*
PA54/ PA134
0
1
1
0
0
0
1
1
1
0
0
PA63/ PA62/ PA61/ PA60/ PA143 PA142 PA141 PA140
0
1
1
0
0
0
1
1
1
0
1
*
*
*
PA64/ PA144
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag set
Note 1) * : Don't care. Note 2) [ NH] : Address of instruction register Note 3) The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
- 54 -
NJU6818
Instruction Table (3)
Instructions
CSb
Code (80 series MPU I/F)
RS RDb WRb RE2 RE1 RE0
Code D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0
Functions Sets palette values to gradation palette A7(PS=0)/A15(PS=1) Sets palette values to gradation palette A7(PS=0)/A15(PS=1) Sets palette values to gradation palette B0(PS=0)/B8(PS=1) Sets palette values to gradation palette B0(PS=0)/B8(PS=1) Sets palette values to gradation palette B1(PS=0)/B9(PS=1) Sets palette values to gradation palette B1(PS=0)/B9(PS=1) Sets palette values to gradation palette B2(PS=0)/B10(PS=1) Sets palette values to gradation palette B2(PS=0)/B10(PS=1) Sets palette values to gradation palette B3(PS=0)/B11(PS=1) Sets palette values to gradation palette B3(PS=0)/B11(PS=1) Sets palette values to gradation palette B4(PS=0)/B12(PS=1) Sets palette values to gradation palette B4(PS=0)/B12(PS=1) Sets palette values to gradation palette B5(PS=0)/B13(PS=1) Sets palette values to gradation palette B5(PS=0)/B13(PS=1)
Gradation palette A7/A15 (Lower) [0H] Gradation palette A7/A15 (Upper) [1H] Gradation palette B0/B8 (Lower) [2H] Gradation palette B0/B8 (Upper) [3H] Gradation palette B1/B9 (Lower) [4H] Gradation palette B1/B9 (Upper) [5H] Gradation palette B2/B10 (Lower) [6H] Gradation palette B2/B10 (Upper) [7H] Gradation palette B3/B11 (Lower) [8H] Gradation palette B3/B11 (Upper) [9H] Gradation palette B4/B12 (Lower) [AH] Gradation palette B4/B12 (Upper) [BH] Gradation palette B5/B13 (Lower) [CH] Gradation palette B5/B13 (Upper) [DH] RE register [FH]
0
1
1
0
0
1
0
PA73/ PA72/ PA71/ PA70/ PA153 PA152 PA151 PA150
0
1
1
0
0
1
0
0
0
0
1
*
*
*
PA74/ PA154
0
1
1
0
0
1
0
0
0
1
0
PB03/ PB02/ PB01/ PB00/ PB83 PB82 PB81 PB80
0
1
1
0
0
1
0
0
0
1
1
*
*
*
PB04/ PG84
0
1
1
0
0
1
0
0
1
0
0
PB13/ PB12/ PB11/ PB10/ PB93 PB92 PB91 PB90
0
1
1
0
0
1
0
0
1
0
1
*
*
*
PB14/ PB94
0
1
1
0
0
1
0
0
1
1
0
PB23/ PB22/ PB21/ PB20/ PB103 PB102 PB101 PB100
0
1
1
0
0
1
0
0
1
1
1
*
*
*
PB24/ PB104
0
1
1
0
0
1
0
1
0
0
0
PB33/ PB32/ PB31/ PB30/ PB113 PB112 PB111 PB110
0
1
1
0
0
1
0
1
0
0
1
*
*
*
PB34/ PB114
0
1
1
0
0
1
0
1
0
1
0
PB43/ PB42/ PB41/ PB40/ PB123 PB122 PB121 PB120
0
1
1
0
0
1
0
1
0
1
1
*
*
*
PB44/ PB124
0
1
1
0
0
1
0
1
1
0
0
PB53/ PB52/ PB51/ PB50/ PB133 PB132 PB131 PB130
0
1
1
0
0
1
0
1
1
0
1
*
*
*
PB54/ PB134
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag set
Note 1) * : Don't care. Note 2) [ NH] : Address of instruction register Note 3) The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
- 55 -
NJU6818
Instruction Table (4)
Instructions
CSb
Code (80 series MPU I/F)
RS RDb WRb RE2 RE1 RE0
Code D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0
Functions Sets palette values to gradation palette B6(PS=0)/B14(PS=1) Sets palette values to gradation palette B6(PS=0)/B14(PS=1) Sets palette values to gradation palette B7(PS=0)/B15(PS=1) Sets palette values to gradation palette B7(PS=0)/B15(PS=1) Sets palette values to gradation palette C0(PS=0)/C8(PS=1) Sets palette values to gradation palette C0(PS=0)/C8(PS=1) Sets palette values to gradation palette C1(PS=0)/C9(PS=1) Sets palette values to gradation palette C1(PS=0)/C9(PS=1) Sets palette values to gradation palette C2(PS=0)/C10(PS=1) Sets palette values to gradation palette C2(PS=0)/C10(PS=1) Sets palette values to gradation palette C3(PS=0)/C11(PS=1) Sets palette values to gradation palette C3(PS=0)/C11(PS=1) Sets palette values to gradation palette C4(PS=0)/C12(PS=1) Sets palette values to gradation palette C4(PS=0)/C12(PS=1)
Gradation palette B6/B14 (Lower) [0H] Gradation palette B6/B14 (Upper) [1H] Gradation palette B7/B15 (Lower) [2H] Gradation palette B7/B15 (Upper) [3H] Gradation palette C0/C8 (Lower) [4H] Gradation palette C0/C8 (Upper) [5H] Gradation palette C1/C9 (Lower) [6H] Gradation palette C1/C9 (Upper) [7H] Gradation palette C2/C10 (Lower) [8H] Gradation palette C2/C10 (Upper) [9H] Gradation palette C3/C11 (Lower) [AH] Gradation palette C3/C11 (Upper) [BH] Gradation palette C4/C12 (Lower) [CH] Gradation palette C4/C12 (Upper) [DH] RE register [FH]
0
1
1
0
0
1
1
PB63/ PB62/ PB61/ PB60/ PB143 PB142 PB141 PB140
0
1
1
0
0
1
1
0
0
0
1
*
*
*
PB64/ PB144
0
1
1
0
0
1
1
0
0
1
0
PB73/ PB72/ PB71/ PB70/ PB153 PB152 PB151 PB150
0
1
1
0
0
1
1
0
0
1
1
*
PC03/ PC83
*
PC02/ PC82
*
PC01/ PC81
PB74/ PB154
0
1
1
0
0
1
1
0
1
0
0
PC00/ PC80
0
1
1
0
0
1
1
0
1
0
1
*
PC13/ PC93
*
PC12/ PC92
*
PC11/ PC91
PC04/ PC84
0
1
1
0
0
1
1
0
1
1
0
PC10/ PC90
0
1
1
0
0
1
1
0
1
1
1
*
*
*
PC14/ PC94
0
1
1
0
0
1
1
1
0
0
0
PC23/ PC22/ PC21/ PC20/ PC103 PC102 PC101 PC100
0
1
1
0
0
1
1
1
0
0
1
*
*
*
PC24/ PC104
0
1
1
0
0
1
1
1
0
1
0
PC33P PC32/ PC31/ PC30/ C113 PC112 PC111 PC110
0
1
1
0
0
1
1
1
0
1
1
*
*
*
PC34/ PC114
0
1
1
0
0
1
1
1
1
0
0
PC43/ PC42/ PC41/ PC40/ PC123 PC122 PC121 PC120
0
1
1
0
0
1
1
1
1
0
1
*
*
*
PC44/ PC124
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag set
Note 1) * : Don't care. Note 2) [ NH] : Address of instruction register Note 3) The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
- 56 -
NJU6818
Instruction Table (5)
Instructions
CSb
Code (80 series MPU I/F)
RS RDb WRb RE2 RE1 RE0
Code D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0
Functions Sets palette values to gradation palette C5(PS=0)/C13(PS=1) Sets palette values to gradation palette C5(PS=0)/C13(PS=1) Sets palette values to gradation palette C6(PS=0)/C14(PS=1) Sets palette values to gradation palette C6(PS=0)/C14(PS=1) Sets palette values to gradation palette C7(PS=0)/C15(PS=1) Sets palette values to gradation palette C7(PS=0)/C15(PS=1) Scan-starting common driver SON : Display clock ON/OFF DSE : Duty-1 ON/OFF
PWM : Variable/Fixed gradation mode C256 : 256-color mode ON/OFF HSW : High speed access ON/OFF ABS : ABS mode ON/OFF CKS : Internal/external oscillation WLS : Display data Length
Gradation palette C5/C13 (Lower) [0H] Gradation palette C5/C13 (Upper) [1H] Gradation palette C6/C14 (Lower) [2H] Gradation palette C6/C14 (Upper) [3H] Gradation palette C7/C15 (Lower) [4H] Gradation palette C7/C15 (Upper) [5H] Initial COM line [6H] Display clock / Duty-1 [7H] Gradation mode control [8H]
Data bus length
0
1
1
0
1
0
0
PC53/ PC52/ PC51/ PC50/ PC133 PC132 PC131 PC130
0
1
1
0
1
0
0
0
0
0
1
*
*
*
PC54/ PC134
0
1
1
0
1
0
0
0
0
1
0
PC63/P PC62/ PC61/ PC60/ C143 PC142 PC141 PC140
0
1
1
0
1
0
0
0
0
1
1
*
*
*
PC64/ PC144
0
1
1
0
1
0
0
0
1
0
0
PC73/ PC72/ PC71/ PC70/ PC153 PC152 PC151 PC150
0
1
1
0
1
0
0
0
1
0
1
*
*
*
PC74/ PC154
0
1
1
0
1
0
0
0
1
1
0
SC3
SC2
SC1
SC0
0 0 0
1 1 1
1 1 1
0 0 0
1 1 1
0 0 0
0 0 0
0 1 1
1 0 0
1 0 0
1 0 1
*
*
DSE SON * *
PWM C256
[9H] EVR control (Lower) [AH] EVR control (Upper) [BH] Frequency control [DH] Discharge ON/OFF [EH] RE register [FH]
Instruction register address
HSW
ABS CKS
WLS
0
1
1
0
1
0
0
1
0
1
0
DV3
DV2
DV1
DV0
Sets EVR level (Lower bit) Sets EVR level (Upper bit) Oscillation frequency Discharge the electric charge in Capacitors on V1 to V4, VLCD
0
1
1
0
1
0
0
1
0
1
1
*
DV6
DV5
DV4
0
1
1
0
1
0
0
1
1
0
1
*
RF2
RF1
RF0
0
1
1
0
1
0
0
1
1
1
0
*
*
DIS2 DIS
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag
[CH]
Instruction register read / ID read
0
1
1
0
1
0
0
1
1
0
0
Register address
Sets instruction register address
0
1
0
1
0/1 0/1 0/1 ID3 ID2 ID1 ID0
Read Data
Read out instruction register data
Note 1) * : Don't care. Note 2) [ NH] : Address of instruction register Note 3) The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set. Note 4) CKS=0: Internal oscillation mode (default) CKS=1: External oscillation mode
- 57 -
NJU6818
Instruction Table (6)
Instructions
CSb
Code (80 series MPU I/F)
RS RDb WRb RE2 RE1 RE0
Code D7 0 D6 0 D5 0 D4 0 D3
EX3
D2
EX2
D1
EX1
D0
EX0
Functions
Window end column address (Lower) [0H] Window end column address (Upper) [1H] Window end row address (Lower) [2H] Window end row address (Upper) [3H] Initial reverse line (Lower) [4H] Initial reverse line (Upper) [5H] Last reverse line (Lower) [6H] Last reverse line (Upper) [7H] Reverse line display ON/OFF [8H] Gradation palette setting [9H] PWM control [AH] RE register [FH]
0
1
1
0
1
0
1
Sets column address for end point
0
1
1
0
1
0
1
0
0
0
1
EX7
EX6
EX5
EX4
Sets column address for end point
0
1
1
0
1
0
1
0
0
1
0
EY3
EY2
EY1
EY0
Sets row address for end point
0
1
1
0
1
0
1
0
0
1
1
*
EY6
EY5
EY4
Sets row address for end point
0
1
1
0
1
0
1
0
1
0
0
LS3
LS2
LS1
LS0
Sets address for reverse line
0
1
1
0
1
0
1
0
1
0
1
*
LS6
LS5
LS4
Sets address for reverse line
0
1
1
0
1
0
1
0
1
1
0
LE3
LE2
LE1
LE0
Sets address for reverse line
0
1
1
0
1
0
1
0
1
1
1
*
LE6
LE5
LE4
Sets address for reverse line
BT : Blink type setting LREV : Reverse line display ON/OFF
0
1
1
0
1
0
1
1
0
0
0
*
*
BT
LREV
0
0
1
1
0
1
0
1
1
0
0
1
*
*
*
PS
PS : Gradation setting
1
1
0
1
0
1
1
0
1
0
PWM PWM PWM PWM S A B C
Sets PWM mode
0
1
1
0
0/1 0/1 0/1
1
1
1
1
TST0 RE2
RE1
RE0 RE flag
Note 1) Note 2) Note 3)
* : Don't care. [ NH] : Address of instruction register The dual instructions including upper and lower bytes is enabled after either upper or lower bytes are set into the register. The only "EVR control" instruction is enabled after both of the upper and lower bytes are set.
- 58 -
NJU6818
(32) Instruction descriptions
This chapter provides detail descriptions and instructions and instruction registers. Nonexistent instruction codes must not be set into the LSI. (32-1) Display data write The "Display data write" instruction is used to write 8-bit display data into the DDRAM.
CSb 0 RS 0 RDb 1
WRb
0
RE2 0/1
RE1 0/1
RE0 0/1
D7
D6
D5
D4 D3 Display data
D2
D1
D0
(32-2) Display data read The "Display data read" instruction is used to read out 8-bit display data from the DDRAM, where the column address and row address must be specified beforehand by the "column address" and "row address" instructions. The dummy read is required just after the "column address" and "row address" instructions.
CSb 0 RS 0 RDb 0
WRb
1
RE2 0/1
RE1 0/1
RE0 0/1
D7
D6
D5
D4 D3 Display data
D2
D1
D0
(32-3) Column address The "column address" instruction is used to specify the column address for display data's reading and writing operations. It requires dual bytes for lower 4-bit and upper 4-bit data. The instruction for the lower 4-bit data must be executed first, next the instruction for the upper 4-bit.
CSb 0 CSb 0 RS 1 RS 1 RDb 1 RDb 1
WRb
0
WRb
RE2 0 RE2 0
RE1 0 RE1 0
RE0 0 RE0 0
D7 0 D7 0
D6 0 D6 0
D5 0 D5 0
D4 0 D4 1
D3 AX3 D3 AX7
D2 AX2 D2 AX6
D1 AX1 D1 AX5
D0 AX0 D0 AX4
0
(32-4) Row address The "row address" instruction is used to specify the row address for display data read and write operations. It requires dual bytes for lower 4-bit and upper 3-bit data. The instruction for the lower 4-bit data must be executed first, next the instruction for the upper 3-bit. The row address is specified in between 00H and 4FH. The setting for nonexistent row address between 50H and FFH is prohibited.
CSb 0 CSb 0 RS 1 RS 1 RDb 1 RDb 1
WRb
0
WRb
RE2 0 RE2 0
RE1 0 RE1 0
RE0 0 RE0 0
D7 0 D7 0
D6 0 D6 0
D5 1 D5 1
D4 0 D4 1
D3 AY3 D3 *
D2 AY2 D2 AY6
D1 AY1 D1 AY5
D0 AY0 D0 AY4
0
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(32-5) Initial display line The "Initial display line" instruction is used to specify the line address corresponding to the initial COM line. The initial COM line is specified by the "Initial COM line" instruction and indicates the common driver that starts scanning display data.
CSb 0 CSb 0 RS 1 RS 1 RDb 1 RDb 1
WRb
0
WRb
RE2 0 RE2 0
RE1 0 RE1 0
RE0 0 RE0 0
D7 0 D7 0
D6 1 D6 1
D5 0 D5 0
D4 0 D4 1
D3 LA3 D3 *
D2 LA2 D2 LA6
D1 LA1 D1 LA5
D0 LA0 D0 LA4
0
LA6 0 0
LA5 0 0
LA4 0 0
LA3 0 0 : : 1
LA2 0 0
LA1 0 0
LA0 0 1
Line address 0 1 : :
1
0
0
1
1
1
79
(32-6) N-line inversion The "N-line inversion" instruction is used to control the alternate rates of liquid crystal direction. It is programmed to select the N value between 2 and 80, and the FR signal toggles once every N lines by setting "1" into the "NLIN" register of the "Display control (2)" instruction. When the N-line inversion is disabled by setting "0" into the "NLIN" register, the FR signal toggles by the frame.
CSb 0 CSb 0 RS 1 RS 1 RDb 1 RDb 1
WRb
0
WRb
RE2 0 RE2 0
RE1 0 RE1 0
RE0 0 RE0 0
D7 0 D7 0
D6 1 D6 1
D5 1 D5 1
D4 0 D4 1
D3 N3 D3 *
D2 N2 D2 N6
D1 N1 D1 N5
D0 N0 D0 N4
0
N6 0 0
N5 0 0
N4 0 0
N3 0 0 : : 1
N2 0 0
N1 0 0
N0 0 1
N value Inhibited 2 : :
1
0
0
1
1
1
80
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N-line Inversion Timing (1/81 duty cycle ratio) N-line inversion OFF
1st line 2nd line 3rd line 80th line 81th line 1st line
CL FLM FR
N-line inversion ON
N-line control
1st line 2nd line 3rd line N line 1st line 2nd line
CL FR
(32-7) Display control (1) The "Display control (1)" instruction is used to control display conditions by setting the "Display ON/OFF", "All pixels ON/OFF", "Display mode" and "Common direction" registers.
CSb 0 RS 1 RDb 1
WRb
RE2 0
RE1 0
RE0 0
D7 1
D6 0
D5 0
D4 0
D3
SHIFT
D2
MON
0
D1 ALL ON
D0 ON/ OFF
ON/OFF register ON/OFF=0 ON/OFF=1 : Display OFF (All COM/SEG output the Vss level.) : Display ON
All ON register The "All pixels ON/OFF" register is used to turn on all pixels without changing display data of the DDRAM. The setting for the "All pixels ON/OFF" register has a priority over the "Reverse display ON/OFF" register. ALLON=0 ALLON=1 MON register MON=0 MON=1 SHIFT register SHIFT=0 SHIFT=1 : COM0 COM79 : COM79 COM0 : Gradation mode : B&W mode : Normal : All pixels turn on.
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(32-8) Display control (2) The "Display control (2)" instruction is used to control display conditions by setting the "Segment direction", "SWAP mode ON/OFF", "N-line inversion ON/OFF" and "Reverse display ON/OFF" registers.
CSb 0 RS 1 RDb 1
WRb
0
RE2 0
RE1 0
RE0 0
D7 1
D6 0
D5 0
D4 1
D3
REV
D2
NLIN
D1
SWAP
D0
REF
REF register The "REF" register is used to reverse the assignment between segment drivers and column address, and it is possible to reduce restrictions for placement of the LSI on the LCD module. For more information, see (10) "The relation among the DDRAM column address, display data and segment drivers". SWAP register The "SWAP" register is used to reverse the arrangement of display data in the DDRAM. SWAP=0 : SWAP mode OFF SWAP=1 : SWAP mode ON (Normal)
SWAP="0" Write data D7 D6 D5 D4 D3 D2 D1 D0
SWAP="1" D7 D6 D5 D4 D3 D2 D1 D0
RAM data
D7 d6 d5 d4 d3 d2 d1 d0
d0 d1 d2 d3 d4 d5 d6 d7
Read data
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
NLIN register The "NLIN" is used to enable or disable the N-line inversion. NLIN=0 : N-line inversion OFF NLIN=1 : N-line inversion ON (The FR signal toggles by the flame.) (The FR signal toggles once every N lines.)
REV register The "REV" register is used to enable or disable the reverse display mode that reverses the polarity of display data without changing display data of the DDRAM. REV=0 REV=1 : Reverse display mode OFF : Reverse display mode ON
REV 0 1 Display Normal Reverse DDRAM data Display data 0 0 1 1 0 1 1 0
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(32-9) Increment control The "Increment control" instruction is used for the increment mode. In using the auto-increment mode, DDRAM address automatically increments (+1) whenever the DDRAM is accessed by the "Display data write" or "Display data read" instruction. Therefore, once "Display data write" or "Display data read" instruction is established, it is possible to continuously access to the DDRAM without the "column address" and "row address" instructions. The settings for the "AIM", "AXI" and "AYI" registers are listed in the following tables.
CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 1 D6 0 D5 1 D4 0 D3 WIN D2 AIM D1 AYI D0 AXI
AIM, AYI and AXI registers
AIM 0 1 Note 1) Note 2) AYI 0 0 1 1 Note 1) Note 2) Increment mode Auto-increment for the both of display data read and write operations Auto-increment for the display write operation (Read-modify-write) It is effective for usual operations accessing successive addresses. It is effective for the read-modify-write operation. AXI 0 1 0 1 Increment mode No auto-increment Auto-increment for the column address Auto-increment for the row address Auto-increment for the column address and row address Note 1 2 3 4 Note 1 2
Auto-increment is disabled regardless of the "AIM" register. Auto-increment of the column address is enabled in accordance with the "AIM" register.
00H
MAXH : CFH : 67H
MAXH in the 8-bit data bus mode MAXH in the 16-bit data bus mode
Note 3)
Auto-increment of the row address is enabled in accordance with the "AIM" register.
00H
4FH
Note 4)
Auto-increments of the column address and the row address are enabled. The row address increments whenever the column address reaches to the MAXH.
00H
MaxH
Column address
MAXH in the 8-bit data bus mode MAXH in the 16-bit data bus mode
4FH 00H Row address
: CFH : 67H
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WIN register The "WIN" register is used to access to the DDRAM for the window display area, where the start point is determined by the "column address" and "row address" instructions, and the end point by the "Window end column address "and "Window end row address" instructions. The setting sequence for the window display area is listed as follows. For more detail, see (6) "Window addressing mode". WIN=0 WIN=1 : Window addressing mode OFF : Window addressing mode ON
1. Set WIN=1, AXI=1, and AYI=1 by the "Increment control" instruction 2. Set the start point by the "column address" and "row address" instructions 3. Set the end point by the "Window end column address" and "Window end row address" instructions 4. Enable to access to the DDRAM in the window addressing mode
START Address
END Address
START Address
END Address
Column address
Row address
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(32-10) Power control
CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 1 D6 0 D5 1 D4 1 D3
AMPON
D2
HALT
D1
DCON
D0
ACL
ACL register The "ACL" register is used to initialize the internal power supply circuits. ACL=0 ACL=1 : Initialization OFF (Normal) : Initialization ON
When the data of the "ACL register" is read out by the "Instruction register read" instruction, the read-out data is "1" during the initialization, and "0" after the initialization. This initialization is performed by using the signal produced by 2 clocks on the OSC1. For this reason, the wait time for 2 clocks of the OSC1 is necessary until next instruction. DCON register The "DCON" register is used to enable or disable the voltage booster. DCON=0 DCON=1 : Voltage booster OFF : Voltage booster ON
HALT register The "HALT" register is used to enable or disable the power save mode. It is possible to reduce operating current down to stand-by level. The internal status in the power save mode is listed below. HALT=0 : Power save OFF (Normal) HALT=1 : Power save ON Internal status in the power save mode * The oscillation circuits and internal power supply circuits are halted. * All segment and common drivers output the VSS level. * The clock input into the OSC1 is inhibited. * The display data in the DDRAM is maintained. * The operational modes before the power save mode are maintained. * The V1 to V4 and the VLCD are in high impedance. As a power save ON sequence, the "Display OFF" must be executed first, next the "Power save ON" instruction, and then all common and segment drivers output the VSS level. And as power save OFF sequence, the "Power save OFF" instruction is executed first, next the "Display ON" instruction. If the "Power save OFF" instruction is executed in the display ON status, unexpected pixels may instantly turn on. AMPON register The "AMPON" register is used to enable or disable the voltage followers, voltage regulator and EVR. AMPON=0 : The voltage followers, the voltage regulator and the EVR OFF AMPON=1 : The voltage followers, the voltage regulator and the EVR ON
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(32-11) Duty cycle ratio The "Duty cycle ratio" instruction is used to select LCD duty cycle ratio for the partial display function. The partial display function specifies some parts of display area on a LCD panel in the condition of lower duty cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage. Therefore, it is possible to optimize the LSI's conditions with extremely low power consumption.
CSb 0 RS 1 RDb 1 DS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WRb 0 DS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RE2 0 RE1 0 RE0 0 DS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D7 1 D6 1 D5 0 D4 0 D3 DS3 D2 DS2 D1 DS1 D0 DS0
DS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Duty cycle ratio DSE=0 DES=1 1/81 1/80 1/77 1/76 1/69 1/68 1/57 1/56 1/47 1/46 1/39 1/38 1/33 1/32 1/27 1/26 1/17 1/16 1/13 1/12 Inhibited Inhibited Inhibited Inhibited Inhibited Inhibited
Row way displays 80 commons 76 commons 68 commons 56 commons 46 commons 38 commons 32 commons 26 commons 16 commons 12 commons
The duty cycle ratio is controlled by the "DS3 to DS0" registers of the "Duty cycle ratio" instruction and the "DSE" register of the "Display clock / Duty-1" instruction. DSE=0 DSE=1 : The number of commons +1 (Duty cycle ratio in the default setting) : The number of commons (Duty-1)
When the "DSE" is "0", all common drivers output non-selective levels in period of lost common. And the segment drivers output the same data for the last line as the data for previous line: For instance they output the same data th st for the 80 and 81 lines when the duty cycle ratio is set to 1/81. For the setting of the "DSE" register, see (32-17) "Display clock / Duty-1". (32-12) Boost level The "Boost level" is used to select multiple of the voltage booster for the partial display function.
CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 1 D6 1 D5 0 D4 1 D3 IDR D2 VU2 D1 VU1 D0 VU0
a) ID read in serial interface ID data can be read out by setting IDR=1. b) Boost level set
VU2 0 0 0 0 1 1 1 1 VU1 0 0 1 1 0 0 1 1 VU0 0 1 0 1 0 1 0 1 Boost level 1-time (No boost) 2-time 3-time 4-time 5-time 6-time Inhibited Inhibited
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(32-13) LCD bias ratio The "LCD bias ratio" is used to select the LCD bias ratio for the partial display function.
CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 0 D7 1 D6 1 D5 1 D4 0 D3 * D2 B2 D1 B1 D0 B0
B2 0 0 0 0 1 1 1 1
B1 0 0 1 1 0 0 1 1
B0 0 1 0 1 0 1 0 1
LCD bias ratio 1/9 1/8 1/7 1/6 1/5 1/4 1/10 Inhibited
(32-14) RE flag The "RE flag" registers are used to determine the contents for the RE registers (RE2, RE1 and RE0), and it is possible to access to the instruction registers. The data of the "TST0" register must be "0", and it is used for maker tests only.
CSb 0 RS 1 RDb 1 WRb 0 RE2 0/1 RE1 0/1 RE0 0/1 D7 1 D6 1 D5 1 D4 1 D3 TST0 D2 RE2 D1 RE1 D0 RE0
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(32-15) Gradation palette A, B and C
CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 1 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 PA03/ PA02/ PA01/ PA00/ PA83 PA82 PA81 PA80
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 0
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PA04/ PA84
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 0
D6 0
D5 1
D4 0
D3 D2 D1 D0 PA13/ PA12/ PA11/ PA10/ PA93 PA92 PA91 PA90
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 0
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0 PA14/ PA94
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 0
D6 1
D5 0
D4 0
D3 D2 D1 D0 PA23/ PA22/ PA21/ PA20/ PA103 PA102 PA101 PA100
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 0
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PA24/ PA104
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 0
D6 1
D5 1
D4 0
D3 D2 D1 D0 PA33/ PA32/ PA31/ PA30/ PA113 PA112 PA111 PA110
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 0
D6 1
D5 1
D4 1
D3 *
D2 *
D1 *
D0 PA34/ PA114
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 1
D6 0
D5 0
D4 0
D3 D2 D1 D0 PA43/ PA42/ PA41/ PA40/ PA123 PA122 PA121 PA120
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CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 0 RE0 1 D7 1 D6 0 D5 0 D4 1 D3 * D2 * D1 * D0 PA44/ PA124
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 1
D6 0
D5 1
D4 0
D3 D2 D1 D0 PA53/ PA52/ PA51/ PA50/ PA133 PA132 PA131 PA130
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 1
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0 PA54/ PA134
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 1
D6 1
D5 0
D4 0
D3 D2 D1 D0 PA63/ PA62/ PA61/ PA60/ PA143 PA142 PA141 PA140
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 0
RE0 1
D7 1
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PA64/ PA144
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 0
D6 0
D5 0
D4 0
D3 D2 D1 D0 PA73/ PA72/ PA71/ PA70/ PA153 PA152 PA151 PA150
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 0
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PA74/ PA154
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 0
D6 0
D5 1
D4 0
D3 D2 D1 D0 PB03/ PB02/ PB01/ PB00/ PB83 PB82 PB81 PB80
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 0
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0 PB04/ PB84
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CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 0 D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 PB13/ PB12/ PB11/ PB10/ PB93 PB92 PB91 PB90
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 0
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PB14/ PB94
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 0
D6 1
D5 1
D4 0
D3 D2 D1 D0 PB23/ PB22/ PB21/ PB20/ PB103 PB102 PB101 PB100
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 0
D6 1
D5 1
D4 1
D3 *
D2 *
D1 *
D0 PB24/ PB104
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 1
D6 0
D5 0
D4 0
D3 D2 D1 D0 PB33/ PB32/ PB31/ PB30/ PB113 PB112 PB111 PB110
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 1
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PB34/ PB114
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 1
D6 0
D5 1
D4 0
D3 D2 D1 D0 PB43/ PB42/ PB41/ PB40/ PB123 PB122 PB121 PB120
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 1
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0 PB44/ PB124
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 0
D7 1
D6 1
D5 0
D4 0
D3 D2 D1 D0 PB53/ PB52/ PB51/ PB50/ PB133 PB132 PB131 PB130
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CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 0 D7 1 D6 1 D5 0 D4 1 D3 * D2 * D1 * D0 PB54/ PB134
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 0
D6 0
D5 0
D4 0
D3 D2 D1 D0 PB63/ PB62/ PB61/ PB60/ PB143 PB142 PB141 PB140
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 0
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PB64/ PB144
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 0
D6 0
D5 1
D4 0
D3 D2 D1 D0 PB73/ PB72/ PB71/ PB70/ PB153 PB152 PB151 PB150
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 0
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0 PB74/ PB154
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 0
D6 1
D5 0
D4 0
D3 D2 D1 D0 PC03/ PC02/ PC01/ PC00/ PC83 PC82 PC81 PC80
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 0
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PC04/ PC84
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 0
D6 1
D5 1
D4 0
D3 D2 D1 D0 PC13/ PC12/ PC11/ PC10/ PC93 PC92 PC91 PC90
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 0
D6 1
D5 1
D4 1
D3 *
D2 *
D1 *
D0 PC14/ PC94
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CSb 0 RS 1 RDb 1 WRb 0 RE2 0 RE1 1 RE0 1 D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 PC23/ PC22/ PC21/ PC20/ PC103 PC102 PC101 PC100
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 1
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PC24/ PC104
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 1
D6 0
D5 1
D4 0
D3 D2 D1 D0 PC33/ PC32/ PC31/ PC30/ PC113 PC112 PC111 PC110
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 1
D6 0
D5 1
D4 1
D3 *
D2 *
D1 *
D0 PC34/ PC114
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 1
D6 1
D5 0
D4 0
D3 D2 D1 D0 PC43/ PC42/ PC41/ PC40/ PC123 PC122 PC121 PC120
CSb 0
RS 1
RDb 1
WRb 0
RE2 0
RE1 1
RE0 1
D7 1
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PC44/ PC124
CSb 0
RS 1
RDb 1
WRb 0
RE2 1
RE1 0
RE0 0
D7 0
D6 0
D5 0
D4 0
D3 D2 D1 D0 PC53/ PC52/ PC51/ PC50/ PC133 PC132 PC131 PC130
CSb 0
RS 1
RDb 1
WRb 0
RE2 1
RE1 0
RE0 0
D7 0
D6 0
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PC54/ PC134
CSb 0
RS 1
RDb 1
WRb 0
RE2 1
RE1 0
RE0 0
D7 0
D6 0
D5 1
D4 0
D3 D2 D1 D0 PC63/ PC62/ PC61/ PC60/ PC143 PC142 PB141 PB140
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CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 0 D6 0 D5 1 D4 1 D3 * D2 * D1 * D0 PC64/ PC144
CSb 0
RS 1
RDb 1
WRb 0
RE2 1
RE1 0
RE0 0
D7 0
D6 1
D5 0
D4 0
D3 D2 D1 D0 PC73/ PC72/ PC71/ PC70/ PC153 PC152 PC151 PC150
CSb 0
RS 1
RDb 1
WRb 0
RE2 1
RE1 0
RE0 0
D7 0
D6 1
D5 0
D4 1
D3 *
D2 *
D1 *
D0 PC74/ PC154
Gradation palette table
Palette value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Gradation level 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31
(Variable gradation mode, PWM="0" and MON="0") (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
Gradation palette Palette 0(default) Palette 1(default) Palette 2(default) Palette 3(default) Palette 4(default) Palette 5(default) Palette 6(default) Palette 7(default) Palette value 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Gradation level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31 Gradation palette Palette 8(default) Palette 9(default) Palette 10(default) Palette 11(default) Palette 12(default) Palette 13(default) Palette 14(default) Palette 15(default)
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NJU6818
(32-16) Initial COM line The "Initial COM line" instruction is used to specify the common driver that starts scanning display data. The line address, corresponding to the initial COM line, is specified by the "Initial display line" instruction.
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 0 D6 1 D5 1 D4 0 D3 SC3 D2 SC2 D1 SC1 D0 SC0
SC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
SC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
SC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
SC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Initial COM line (SHIFT=0) COM0 COM4 COM8 COM16 COM24 COM32 COM40 COM48 COM56 COM64 COM72 Inhibited Inhibited Inhibited Inhibited Inhibited
Initial COM line (SHIFT=1) COM79 COM75 COM71 COM63 COM55 COM47 COM39 COM31 COM23 COM15 COM7 Inhibited Inhibited Inhibited Inhibited Inhibited
SHIFT=0: Positive scan direction SHIFT=1: Negative scan direction
(COM0 COM79) (COM79 COM0)
(32-17) Display clock / Duty-1 The "Display clock / Duty-1" instruction is used to enable or disable the display clocks (CL, FLM, FR, and CLK), and to control ON/OFF of the "Duty-1". For more detail about the "Duty-1", see (32-11) "Duty cycle ratio".
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 0 D6 1 D5 1 D4 1 D3 * D2 * D1 DSE D0 SON
SON=0: SON=1: DSE=0: DSE=1:
CL, FLM, FR, and CLK are level "0" CL, FLM, FR, and CLK outputs are active. Duty-1 OFF Duty-1 ON
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NJU6818
(32-18) Gradation mode control The "Gradation mode control" is used to select display mode as follows.
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 0 D5 0 D4 0 D3 D2 PWM C256 D1 * D0 *
PWM register PWM=0: Variable gradation mode (Variable 16-gradation levels out of 32-gradation level of the gradation palette) PWM=1: Fixed gradation mode (Fixed 8-gradation levels) C256 register C256=0 256-color mode OFF (4,096-color in the default setting) C256=1 256-color mode ON
(32-19) Data bus length The "Data bus length" instruction is used to select 8- or 16- bit data bus length and determine the internal or external oscillation. In the 16-bit data bus mode, instruction data must be 16-bit (D15 to D0) as well as display data. However, for the access to the instruction registers, the lower 8-bit data (D7 to D0) of the 16-bit data is valid. For the access to the DDRAM, all of the 16-bit data (D15 to D0) is valid.
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 0 D5 0 D4 1 D3 HSW D2 ABS D1 CKS D0 WLS
HSW register HSW =0 :High speed access mode OFF HSW=1 :High speed access mode ON (only in the 8-bit data bus length) ABS register ABS=0 ABS=1 WLS register WLS=0 :8-bit data bus length WLS =1 :16-bit data bus length CKS register CKS =0 :Internal oscillation (The OSC1 terminal must be fixed "1" or "0".) CKS =1 :External oscillation (By the external clock into the OSC1 or external resister between the OSC1 and OSC2. OSC2 should be open when clock is inputted from OSC1.) :ABS mode OFF (normal) :ABS mode ON
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NJU6818
(32-20) EVR control The "EVR control" instruction is used to fine-tune the LCD driving voltage (VLCD), so that it is possible to optimize contrast level for a LCD panel. This instruction must be programmed by upper 3-bit data first, next lower 4-bit data. And it becomes enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the VLCD from being generated.
CSb 0 CSb 0 RS 1 RS 1 RDb 1 RDb 1 DV6 0 0 1 WRb 0 WRb 0 DV5 0 0 1 RE2 1 RE2 1 RE1 0 RE1 0 RE0 0 RE0 0 DV2 0 0 1 D7 1 D7 1 DV1 0 0 1 D6 0 D6 0 DV0 0 1 1 D5 1 D5 1 D4 0 D4 1 D3 DV3 D3 * D2 DV2 D2 DV6 D1 DV1 D1 DV5 D0 DV0 D0 DV4
DV4 0 0 1
DV3 0 0 : : 1
VLCD Low : : : High
The formula of the VLCD is shown below. VLCD [V] = 0.5 x VREG + M (VREG - 0.5 x VREG) / 127 VBA = VEE x 0.9 VREG = VREF x N VBA VREF VREG N M : Output voltage of the reference voltage generator : Input voltage of the voltage regulator : Output voltage of the voltage regulator : Register value for the voltage booster : Register value for the EVR
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NJU6818
(32-21) Frequency control The "Frequency control" instruction is used to control the frame frequency for a LCD panel.
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 1 D5 0 D4 1 D3 * D2 Rf2 D1 Rf1 D0 Rf0
Rfx register (x=0, 1, 2) The "Rfx" register is used to determine the feed back resister value for the internal oscillator, and it is possible to adjust the frame frequency for the LCD modules.
Rf 2 0 0 0 0 1 1 1 1 Rf 1 0 0 1 1 0 0 1 1 Rf 0 0 1 0 1 0 1 0 1 Feedback resistor value Reference value 0.8 x reference value 0.9 x reference value 1.1 x reference value 1.2 x reference value 0.7 x reference value 1.3 x reference value Inhibited
(32-22) Discharge ON/OFF Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and the VLCD terminals. The "Discharge ON/OFF" instruction is usually required just after the internal power supply is turned off by setting "0" into the "DCON" and "AMPON" registers, or just after the external power supply is turned off. During the discharge operation, the internal or external power supply must not be turned on.
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 1 D5 1 D4 0 D3 * D2 * D1 DIS2 D0 DIS
DIS=0: DIS=1: DIS2=0: DIS2=1:
Discharge OFF Discharge ON Discharge OFF Discharge ON
(Capacitors on the VLCD, V1, V2, V3 and V4) (Capacitors on the VLCD, V1, V2, V3 and V4) (Resistance between VOUT and VEE) (Resistance between VOUT and VEE)
Note ) VOUT and VEE are internally connected with the resistor (100k typical) in the power-ON.
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NJU6818
(32-23) Instruction register address The "Instruction register address" is used to specify the instruction register address, so that it is possible to read out the contents of the instruction registers in combination with the "Instruction register read" instruction.
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 0 D7 1 D6 1 D5 0 D4 0 D3 RA3 D2 RA2 D1 RA1 D0 RA0
(32-24) Instruction register read / ID read The "Instruction register read" instruction is used to read out the contents of the instruction register in combination with the "Instruction register address" instruction. Upper 4-bit of the read-out data is assigned to the ID data.
CSb 0 RS 1 RDb 0 WRb 1 RE2 0/1 RE1 0/1 RE0 0/1 D7 ID3 D6 ID2 D5 ID1 D4 ID0 D3 D2 D1 D0 Internal register data read
(32-25) Window end column address The "Window end column address" is used to specify the column address for the window end point. The lower 4bit data is required to be programmed first and then the upper 3-bit data can be programmed.
CSb 0 CSb 0 RS 1 RS 1 RDb 1 RDb 1 WRb 0 WRb 0 RE2 1 RE2 1 RE1 0 RE1 0 RE0 1 RE0 1 D7 0 D7 0 D6 0 D6 0 D5 0 D5 0 D4 0 D4 1 D3 EX3 D3 EX7 D2 EX2 D2 EX6 D1 EX1 D1 EX5 D0 EX0 D0 EX4
(32-26) Window end row address set The "Window end row address" is used to specify the row address for the window end point. The lower 4-bit data is required to be programmed first and then the upper 3-bit data can be programmed.
CSb 0 CSb 0 RS 1 RS 1 RDb 1 RDb 1 WRb 0 WRb 0 RE2 1 RE2 1 RE1 0 RE1 0 RE0 1 RE0 1 D7 0 D7 0 D6 0 D6 0 D5 1 D5 1 D4 0 D4 1 D3 EY3 D3 * D2 EY2 D2 EY6 D1 EY1 D1 EY5 D0 EY0 D0 EY4
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NJU6818
(32-27) Initial reverse line The "Initial reverse line" instruction is used to specify the initial reverse line address for the reverse line display. Lower 4-bit data must be programmed first, next upper 3-bit data. It is programmed in between 00H and 4FH and the line address beyond 4FH is inhibited. The address relation: LSi < LEi (i=7 to 0) must be maintained in the reverse line display.
CSb 0 CSb 0 RS 1 RS 1 RDb 1 RDb 1 WRb 0 WRb 0 RE2 1 RE2 1 RE1 0 RE1 0 RE0 1 RE0 1 D7 0 D7 0 D6 1 D6 1 D5 0 D5 0 D4 0 D4 1 D3 LS3 D3 * D2 LS2 D2 LS6 D1 LS1 D1 LS5 D0 LS0 D0 LS4
(32-28) Last reverse line The "Last reverse line" instruction is used to specify the last reverse line address for the reverse line display. Lower 4-bit data must be programmed first, next upper 3-bit. It is programmed in between 00H and 4FH and the line address beyond the 4FH is inhibited. The address relation: LSi < LEi (i=7 to 0) must be maintained in the reverse line display.
CSb 0 CSb 0 RS 1 RS 1 RDb 1 RDb 1 WRb 0 WRb 0 RE2 1 RE2 1 RE1 0 RE1 0 RE0 1 RE0 1 D7 0 D7 0 D6 1 D6 1 D5 1 D5 1 D4 0 D4 1 D3 LE3 D3 * D2 LE2 D2 LE6 D1 LE1 D1 LE5 D0 LE0 D0 LE4
(32-29) Reverse line display ON/OFF The "Reverse line display ON/OFF" is used to enable or disable the reverse line display for the blink operation and determine the reverse line display mode.
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 1 D6 0 D5 0 D4 0 D3 * D2 * D1 BT D0 LREV
LREV register The "LREV" register is used to enable or disable the reverse line display. LREV =0: LREV =1: Reverse line display OFF (Normal) Reverse line display ON
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NJU6818
BT register The "BT" register is used to determine the reverse line display mode in the reverse line display ON (LREV=1) status. BT =0: BT =1: Normal reverse line display Blink once every 32 frames Display examples in the LREV="1" and BT="1"
Blink once every 32 frames
NJRC LCD DRIVER Low Power and Low Voltage
Blink once every 32 frames
NJRC LCD DRIVER Low Power and Low Voltage
Initial reverse line address Last reverse line address
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NJU6818
(32-30) Gradation Palette setting control
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 1 D6 0 D5 0 D4 1 D3 * D2 * D1 * D0 PS
PS register PS=0: PS=1: Lower 8 Gradation setting Upper 8 Gradation setting
(32-31) PWM control The "PWM control" is used to determine the PWM type for segment waveforms, where the type can be specified for each of the SEGAi, SEGBi and SEGCi (i=0-103) drivers.
CSb 0 RS 1 RDb 1 WRb 0 RE2 1 RE1 0 RE0 1 D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0
PWMS PWMA PWMB PWMC
PWMS register PWMS=0: Type 1 PWMS=1: Type 2 PWMA, B and C registers The "PWMA, PWMB and PWMC" registers are used to select the type 1-O or type 1-E. PWMZ=0 (Z=A, B and C): Type 1-O PWMZ=1 (Z=A, B and C): Type 1-E PWM type1 (PWMS="0") "H" CL "L" VLCD Type-O SEG VLCD Type-E V2 V2 Odd line Even line
PWM type2 (PWMS="1") CL "H" "L"
SEG
VLCD V2
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NJU6818
(33) The relation between Common drivers and Row addresses
Row address assignment of common drivers is programmed by the "SHIFT" register of the "Display control (1)", "Duty cycle ratio", "Initial display line" and "Initial COM line" instructions. When initial display line is "0" If the "SHIFT" is "0", the scan direction is normal. When the "LA0 to LA6" registers of the "Initial display line" instruction is "0", the "MY" corresponding to the initial COM line is "0" and is increasing during display. When initial display line is not "0" If the "SHIFT" is "1", the scan direction is inversed. When the "LA0 to LA6" registers of the "Initial display line" instruction is not "0", the "MY" corresponding to the initial COM line is this setting value and is increasing during display. The followings are examples of setting the start-line 0 or 5 at 1/81, or 1/13 duty.
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NJU6818
(33-1) Initial display line "0", 1/81 duty cycle (Common forward scan)
SC3 SC2 SC1 SHIFT="0"(Common forward scan), DS3, 2, 1, 0="0000", LA6....LA0="00000000"(Initial display line 0) SC0 0000 0001 0010 0011 0100 0101 0110 0111 1000
0 76 72 64 56 48 40 32 24
1001
16
1010
8
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 (81th COM period) *1
79 0
79 0
79 0
79 0
79 0
79 0
79 0
79 0
79 0
79 0
79 79
75 79
71 79
63 79
55 79
47 79
39 79
31 79
23 79
15 79
7 79
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line *1 : 81th COM period is not selected.
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NJU6818
(33-2) Initial display line "0", 1/13 duty cycle (Common forward scan)
SC3 SC2 SC1 SHIFT="0"(Common forward scan), DS3, 2, 1, 0="1001", LA6....LA0="00000000"(Initial display line 0) SC0 0000 0001 0010 0011 0100 0101 0110 0111 1000
0
1001
1010
8
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 (13th COM period) *1
11 0
0
11
11 0
11
0
11
0
11
0
11
0
11
0
11
0
11
0
11
11
11
11
11
11
11
11
11
11
11
7 11
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line *1 : 13th COM period is not selected.
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NJU6818
(33-3) Initial display line "0", 1/81 duty cycle (Common backward scan)
SC3 SC2 SC1 SHIFT="1"(Common backward scan), DS3, 2, 1, 0="0000", LA6....LA0="00000000"(Initial display line 0) SC0 0000 0001 0010 0011 0100 0101 0110 0111 1000
79 75 71 63 55 47 39 31 23
1001
15
1010
7
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 (81th COM period) *1
0 79
0 79
0 79
0 79
0 79
0 79
0 79
0 79
0 79
0 79
0 79
76 79
72 79
64 79
56 79
48 79
40 79
32 79
24 79
16 79
8 79
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line *1 : 81th COM period is not selected.
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NJU6818
(33-4) Initial display line "5", 1/81 duty cycle (Common forward scan)
SC3 SC2 SC1 SHIFT="0"(Common forward scan), DS3, 2, 1, 0="0000", LA6....LA0="00000101"(Initial display line 5) SC0 0000 0001 0010 0011 0100 0101 0110 0111 1000
5 1 77 78 79 0 69 61 53 45 37 29
1001
21
1010
13
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 (81th COM period) *1
5
5 79 0
5 79 0
5 79 0
5 79 0
5 79 0
5 79 0
5 79 0
5 79 0
5 79 0
4 79
79 0 79
76 79
68 79
60 79
52 79
44 79
36 79
28 79
20 79
12 79
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line *1 : 81th COM period is not selected.
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NJU6818
(33-5) Initial display line "0", 1/80 duty cycle (Common forward scan, DSE="1")
SC3
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79
SC2
SHIFT="0"(Common forward scan), DS3, 2, 1, 0="0000", LA6....LA0="00000000"(Initial display line 0) DSE="1" SC1 SC0 0000 0001 0010 0011 0100 0101 0110 0111 1000
0 76 72 64 56 48 40 32 24
1001
16
1010
8
79 0
79 0
79 0
79 0
79 0
79 0
79 0
79 0
79 0
79 0
79
75
71
63
55
47
39
31
23
15
7
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
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NJU6818
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Supply Voltage (4) Supply Voltage (5) Supply Voltage (6) Input Voltage Storage Temperature SYMBOL VDD VEE VOUT VREG VLCD V1, V2, V3, V4 VI Tstg CONDITION TERMINAL VDD VEE VOUT VREG VLCD V1, V2, V3, V4 *1 RATING -0.3 to +4.0 -0.3 to +4.0 -0.3 to +19.0 -0.3 to +19.0 -0.3 to +19.0 -0.3 to VLCD + 0.3 -0.3 to VDD + 0.3 -45 to +125 UNIT V V V V V V V C
VSS=0V Ta = +25C
Note 1) D0 to D15, CSb, RS, RDb, WRb, OSC1, RESb, TEST1, TEST2, terminals.
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply Voltage SYMBOL VDD1 VDD2 VEE VLCD VOUT VREG VREF Topr TERMINAL VDD VEE VLCD VOUT VREG VREF MIN 1.7 2.4 2.4 5 TYP MAX 3.3 3.3 3.3 18.0 18.0 VOUT x 0.9 3.3 85 UNIT V V V V V V V C NOTE *1 *2 *3 *4
Operating Voltage Operating Temperature
2.1 -30
*5
Applies to the condition when the reference voltage generator is not used. Applies to the condition when the reference voltage generator is used. Applies to the condition when the voltage booster is used. The following relation among the supply voltages must be maintained. VSSNote1) Note2) Note3) Note4)
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NJU6818
DC CHARACTERISTICS 1
VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85C PARAMETER High level input voltage Low level input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage Input leakage current Output leakage current Driver ON-resistance Stand-by current Internal oscillation Frequency External oscillation Frequency Voltage converter output voltage Supply current (1) Supply current (2) Supply current (3) Supply current (4) Supply current (5) Supply current (6) VBA Operating voltage VREG Operating voltage
SYM BOL VIH VIL VOH1 VOL1 VOH2 VOL2 ILI ILO RON1 ISTB fOSC1 fOSC2 fOSC3 fr1 fr2 fr3 VOUT IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 VBA VREG V2 V3 VD12 VD34 VD24
CONDITION
MIN 0.8 VDD 0 VDD - 0.4 VDD - 0.4 -10 -10
TYP
MAX VDD 0.2VDD 0.4 0.4 10 10 2 4 15 445 101 14.4
UNIT NOTE V V V V V V A A k A kHz *1 *1 *2 *2 *3 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12
IOH = -0.4mA IOL = 0.4mA IOH = -0.1mA IOL = 0.1mA VI = VSS or VDD VI = VSS or VDD |VON| = 0.5V
VLCD = 10V VLCD = 6V
1 2 309 69 10.0 377 85 12.2 382 84 12.8
CSb=VDD, Ta=25C VDD = 3V VDD = 3V Ta = 25C Rf=24k Rf=120k Rf=820k N-time booster (N=2 to 6) RL = 500k (VOUT - VSS) VDD = 3V, 6-time booster Whole ON pattern VDD = 3V, 6-time booster Checker pattern VDD = 3V, 5-time booster Whole ON pattern VDD = 3V, 5-time booster Checker pattern VDD = 3V, 4-time booster Whole ON pattern VDD = 3V, 4-time booster Checker pattern VEE = 2.4 to 3.3V VEE = 2.4 to 3.3V VREF = 0.9 x VEE N-time booster (N=2 to 6)
kHz V
(N x VEE) x 0.95 760 930 520 650 360 450 (0.9 VEE) x 0.98
(VREF x N)
1140 1400 780 980 540 680 (0.9 VEE) x 1.02
(VREF x N)
A
*13
0.9 VEE
(VREF x N)
V V
*14 *15
x 0.97 -100 -100 -30 -30 -30
x 1.03 +100 +100 +30 +30 +30
Output Voltage
0 0 0 0 0
mV
*16
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NJU6818
CLOCK and FRAME FREQUENCY
Display duty cycle ratio (1/D)
1/81 to 1/57 1/47 to 1/27 1/17, 1/13
PARAMETER SYMBOL
Display mode 16 Gradation mode
NOTE
fOSC / (62xD) fOSC / (14xD) fOSC / (2xD) fCK / (62xD) fCK / (14xD) fCK / (2xD)
fOSC / (62xDx2) fOSC / (14xDx2) fOSC / (2xDx2) fCK / (62xDx2) fCK / (14xDx2) fCK / (2xDx2)
fOSC / (62xDx4) fOSC / (14xDx4) fOSC / (2xDx4) FLM fCK / (62xDx4) fCK / (14xDx4) fCK / (2xDx4)
Internal clock
fOSC
Simplified 8 gradation mode B&W mode 16 Gradation mode
External clock
fCK
Simplified 8 gradation mode B&W mode
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NJU6818
APPLIED TERMINALS and CONDITIONS
Note 1) Note 2) Note 3) Note 4) Note 5) Note 6) D0-D15, CSb, RS, RDb, WRb, P/S, SEL68, RESb D0-D15 CL, FLM, FR, CLK CSb, RS, SEL68, RDb, WRb, P/S, RESb, OSC1 D0-D15 in high impedance SEGA0-SEGA103, SEGB0-SEGB103, SEGC0-SEGC103, COM0-COM79 - Defines the resistance between the COM/SEG terminals and the power supply terminals (VLCD, V1, V2, V3 and V4) at the condition of 0.5V deference and 1/9 LCD bias ratio VDD - The oscillator is halted, CSb="1" (disabled), No-load on the COM/SEG drivers OSC - Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the variable gradation mode OSC - Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the fixed gradation mode
Note 7) Note 8) Note 9)
Note 10) OSC - Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the Black & White mode Note 11) VDD=3V, Ta=25C Note 12) VOUT - Applies to the condition when the internal voltage booster, the internal oscillator and the internal power circuits are used - VEE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1), 1/4 to 1/10 LCD bias, 1/81 duty cycle, No-load on the COM/SEG drivers - RL=500k between the VOUT and the VSS, CA1=CA2=1.0uF, CA3=0.1uF, DCON="1", AMPON="1" Note 13) VDD - Applies to the condition using the internal oscillator and the internal power circuits, no access between the LSI and MPU - EVR= (1,1,1,1,1,1,1), All pixels turned-on or checkerboard display in the gradation mode, No-load on the COM/SEG drivers - VDD=VEE, VREF=0.9VEE, CA1=CA2=1.0uF, CA3=0.1uF, DCON="1", AMPON="1", NLIN="0", 1/81 Duty cycle, Ta=25C Note 14) VBA - Applies to the condition that VBA=VREF and the voltage booster N= 1, DCON="0", VOUT=13.5V input. Note 15) VREG - VEE=2.4V to 3.3V, VREF=0.9VEE, VOUT=18V, 1/4 to 1/10 LCD bias ratio, 1/81 duty cycle, EVR=(1,1,1,1,1,1,1), - Checkerboard display, No-load on the COM/SEG drivers, the voltage booster N=2 to 6, CA1=CA2=1.0uF, CA3=0.1uF, DCON="0", AMPON="1", NLIN="0" Note 16) VLCD, V1, V2, V3, V4 - VEE=3.0V, VREF=0.9VEE, VOUT=15V, 1/4 to 1/10 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF, No-load on the COM/SEG drivers, voltage booster N=5, CA1=CA2=1.0uF, CA3=0.1uF, DCON="0", AMPON="1"
(1) (2) (3) (4)
VLCD V1 V2 V3 V4 VSS
VD12: (1)-(2) VD34: (3)-(4) VD24: (2)-(4)
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NJU6818
AC CHARACTERISTICS
Write operation (80-type MPU) tAS8 CSb RS
tAH8
WRb
tWRLW8
tWRHW8 tDS8 tDH8
D0 to D15 tCYC8
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8
CONDITION
MIN. 0 0 90 35 35 30 5
(VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns ns ns CSb RS
WRb D0 to D15
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8
CONDITION
MIN. 0 0 160 70 70 40 5
(VDD=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns ns ns CSb RS
WRb D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8 CONDITION MIN. 0 0 180 80 80 70 10 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS
WRb D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
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NJU6818
Read operation (80-type MPU) tAS8 CSb RS tAH8
RDb
tWRLR8
tWRHR8 tRDH8
D0 to D15 tRDD8 tCYC8
(VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 60 0 ns ns CSb RS RDb
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8
CONDITION
MIN. 0 0 180 80 80
CL=15pF
D0 to D15
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8
CONDITION
MIN. 0 0 180 80 80
(VDD=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 60 ns ns CSb RS RDb
CL=15pF
0
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8 CL=15pF CONDITION MIN. 0 0 300 140 140 130 0 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS RDb
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
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NJU6818
Write operation (68-type MPU) tAS6 CSb RS R/W (WRb) tAH6
E (RDb)
tEHW6 tDS6 tDH6
tELW6
D0 to D15 tCYC6
(VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns ns ns CSb RS E
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6
CONDITION
MIN. 0 0 90 35 35 40 5
D0 to D15
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6
CONDITION
MIN. 0 0 160 70 70 50 5
(VDD=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns ns ns CSb RS E
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Data setup time Data hold time SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 CONDITION MIN. 0 0 180 80 80 70 10 MAX. UNIT ns ns ns ns ns ns ns TERMINAL CSb RS E
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
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NJU6818
Read operation (68-type MPU) tAS6 CSb RS tAH6
R/W (WRb) tELR6 E (RDb) tRDH6 tEHR6
D0 to D15 tRDD6 tCYC6
(VDD=2.5 to 3.3V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 70 ns ns CSb RS E
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6
CONDITION
MIN. 0 0 180 80 80
CL=15pF
0
D0 to D15
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6
CONDITION
MIN. 0 0 180 80 80
(VDD=2.2 to 2.5V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 70 ns ns CSb RS E
CL=15pF
0
D0 to D15
PARAMETER Address hold time Address setup time System cycle time Enable "L" level pulse width Enable "H" level pulse width Read Data delay time Read Data hold time
SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6
CONDITION
MIN. 0 0 300 140 140
(VDD=1.7 to 2.2V, Ta=-30 to +85C) MAX. UNIT TERMINAL ns ns ns ns ns 130 ns ns CSb RS E
CL=15pF
0
D0 to D15
Note) Each timing is specified based on 20% and 80% of VDD.
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NJU6818
Serial interface CSb tCSS tCSH
RS tASS SCL tSHW tCYCS tSLW tAHS
tDSS
tDHS
SDA
(VDD=2.5 to 3.3V, Ta=-30 to +85C) PARAMETER Serial clock cycle SCL "H" level pulse width SCL "H" level pulse width 2 SCL "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSb - SCL time CSb hold time SYMBOL tCYCSB tSHW tSHW2 tSLW tASS tAHS tDSS tDHS tCSS tCSH CONDITION MIN. 50 20 300 20 20 20 20 20 20 20 MAX. UNIT ns ns ns ns ns ns ns ns ns ns TERMINAL SCL RS SDA CSb
Note 2)
(VDD=2.2 to 2.5V, Ta=-30 to +85C) PARAMETER Serial clock cycle SCL "H" level pulse width SCL "H" level pulse width 2 SCL "L" level pulse width Address setup time Address hold time Data setup time Data hold time CSb - SCL time CSb hold time SYMBOL tCYCS tSHW tSHW2 tSLW tASS tAHS tDSS tDHS tCSS tCSH CONDITION MIN. 50 20 400 20 20 20 20 20 20 20 MAX. UNIT ns ns ns ns ns ns ns ns ns ns TERMINAL SCL RS SDA CSb
Note 2)
(VDD=1.7 to 2.2V, Ta=-30 to +85C) PARAMETER Serial clock cycle SCL "H" level pulse width SCL "H" level pulse width 2 SCL "L" level pulse width Address setup time Address hold time Data setup time Data hold time SYMBOL tCYCS tSHW tSHW2 tSLW tASS tAHS tDSS tDHS CONDITION MIN. 80 35 500 35 35 35 35 35 MAX. UNIT ns ns ns ns ns ns ns ns TERMINAL SCL RS SDA
Note 2)
CSb - SCL time tCSS 35 ns CSb tCSH 35 ns CSb hold time Note) Each timing is specified based on 20% and 80% of VDD. Note 2) tSHW2 applies to the condition when the ID read-out. Refer to the (18) "Chip Identification" for the detail.
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NJU6818
Display control timing CLK
tDCL
CL tDFLM tDFLM FLM tFR FR
Output timing PARAMETER FLM delay time FR delay time CL delay time SYMBOL tDFLM tFR tDCL CONDITION CL=15pF MIN. 0 0 0
(VDD=2.4 to 3.3V, Ta=-30 to +85C) MAX. 500 500 200 UNIT ns ns ns TERMINAL FLM FR CL
Output timing PARAMETER SYMBOL CONDITION FLM delay time tDFLM CL=15pF FR delay time tFR CL delay time tDCL Note) Each timing is specified based on 20% and 80% of VDD. MIN. 0 0 0
(VDD=1.7 to 2.4V, Ta=-30 to +85C) MAX. 1000 1000 200 UNIT ns ns ns TERMINAL FLM FR CL
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NJU6818
Input clock timing tCKLW OSC1 tCKHW
PARAMETER OSC1 "H" level pulse width (1) OSC1 "L" level pulse width (1) OSC1 "H" level pulse width (2) OSC1 "L" level pulse width (2) OSC1 "H" level pulse width (3) OSC1 "L" level pulse width (3)
SYMBOL tCKHW1 tCKLW1 tCKHW2 tCKLW2 tCKHW3 tCKLW3
CONDITION
MIN. 1.12 1.12 4.95 4.95 34.7 34.7
MAX. 1.62 1.62 7.25 7.25 50.0 50.0
(VDD=1.7 to 3.3V, Ta=-30 to +85C) UNIT TERMINAL OSC1 s 1 s OSC1 s 2 s OSC1 s 3 s
Note) Each timing is specified based on 20% and 80% of VDD. Note 1) Applied to the variable gradation mode /MON="0",PWM="0" Note 2) Applied to the fixed gradation mode /MON="0",PWM="1" Note 3) Applied to the B&W mode /MON="1"
Reset input timing tRW
RESb
tR Internal circuit status
During reset
End of reset
PARAMETER Reset time RESb "L" level pulse width
SYMBOL tR tRW
CONDITION
MIN.
(VDD=2.4 to 3.3V, Ta=-30 to +85C) UNIT MAX. Terminal 1.0 s s RESb
10.0
PARAMETER Reset time RESb "L" level pulse width
SYMBOL tR tRW
CONDITION
MIN.
(VDD=1.7 to 2.4V, Ta=-30 to +85C) UNIT MAX. Terminal 1.5 s s RESb
10.0
Note) Each timing is specified based on 20% and 80% of VDD.
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NJU6818
Typical characteristic
PARAMETER Basic delay time of gate SYMBOL Ta=+25C, VSS=0V, VDD=3.0V MIN TYP 10 MAX UNIT ns
Input output terminal type (a) Input circuit VDD I VSS(0V) Terminals: CSb, RS, RDb, WRb, SEL68, P/S, RESb
Input signal
(b) Output circuit VDD Terminals: FLM, CL, FR, CLK
O VSS(0V)
Output control signal Output signal
(c) Input/Output circuit VDD I/O VSS(0V) VSS(0V) Input control signal VDD Output control signal Output signal VSS(0V) Terminals: D0 to D15
Input signal
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NJU6818
(d) Display output circuit VLCD Output control signal 1 O Output control signal 3 VSS(0V) V3/V4 VSS(0V) Output control signal 4 VSS(0V) VLCD VLCD V1/V2 Output control signal 2
Terminals:
SEGA0 to SEGA103 SEGB0 to SEGB103 SEGC0 to SEGC103 COM0 to COM79
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NJU6818
APPLICATION CIRCUIT EXAMPLES
(1) MPU Connections 80-type MPU interface 1.7V to 3.3V
A0 A1 to A7 7 (80-type MPU) IORQb D0 to D7 RDb WR GND RESb
VCC
RS Decoder 8 CSb
VDD
D0 to D7 RDb WRb RESb V SS
RESET
68-type MPU interface
1.7V to 3.3V
VCC
A0 15 Decoder 8
RS CSb
VDD
A1 to A15 (68-type MPU) VMA D0 to D7 E R/W RESb GND
D0 to D7 RDb(E) WRb(R/W) RESb VSS
RESET
Serial interface 1.7V to 3.3V
VCC (MPU)
A0 A1 to A7 7 Decoder
RS CSb
VDD
PORT1 PORT2 RESb GND RESET
SDA SCL RESb VSS
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NJU6818
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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